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BI Jinshun
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Update time: 2016-11-18
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Name:BI Jinshun

Gender:Male

Title:Associate Researcher

Nationality:P.R.China

Education:PhD

E-Mail: bijinshun@ime.ac.cn

Department:Key Laboratory of Microelectronics Devices & Integrated Technology , Institute of Microelectronics, Chinese Academy of Sciences

Address:3 Beitucheng West Road, Chaoyang District, Beijing, PR China

Postcode:100029

Tel.:+86-10-82995940

Fax:+86-10-82995583

Education Background:

Ph.D. Institute of Microelectronics, Chinese Academy of Sciences 2005-2008

Research: SOI technology, device, radiation effects and harden techniques

M.Sc. Institute of Microelectronics, Chinese Academy of Sciences 2003-2005

Research: SOI technology, device, radiation effects and harden techniques

B.Sc. Electrical Engineering, Nankai University, Tianjin, China 1999-2003

Specializations: Microelectronics

Professional Experience:

  1. Radio Frequency and radiation hardened SOI CMOS processes and devices
  2. SOI CMOS SPICE modeling and extraction
  3. Process control monitor and reliability evaluation patterns design
  4. Standard cell library and IC design
  5.  Radiation effects on emerging semiconductor devices, such as UTB FDSOI, FinFET, Flash and ReRAM
  6. Semiconductor radiation effects failure mechanism and evaluation methods

Research Interests:

Radiation effects and hardening techniques of semiconductor devices and circuits

Publications:

SCI journal papers:

1.        Yi Ren, Li Chen, Jinshun Bi, An RHBD Bandgap Reference Utilizing Single Event Transient Isolation Technique, IEEE Transactions on Nuclear Science, 2016, Vol. 63, No. 3, P. 1927 – 1933

2.        Bingqing Xie, Bo Li, Jinshun Bi, Jianhui Bu, Chi Wu, Binhong Li, Zhengsheng Han, Jiajun Luo, Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices, Chinese Physics B, 2016, Vol. 25, No. 7, P. 078501

3.        Xing Zhao,Bo Mei,Jinshun Bi,Zhongshan Zheng,Linchun Gao,Chuanbin Zeng,Jiajun Luo,Fang Yu,Zhengsheng Han,Single event transients in a 0.18 μm partially-depleted silicon-on-insulator complementary metal oxide semiconductor circuit,Acta Phys. Sin,2015,Vol. 64, No. 13, P. 136102

4.        H. B. Wang, R. Liu, L. Chen, J. S. Bi, M. L. Li, Y. Q. Li, A Novel Built-in Current Sensor for N-WELL SET Detection, Journal of Electronic Testing, 2015, Vol. 31, No. 4, P. 395-401

5.        S. Gu, J. Liu, F. Z. Zhao, Z. G. Zhang, J. S. Bi, C. Geng. G. Liu, M. D. Hou, T. Q. Liu, Y. M. Sun, J. Luo, and K. Xi, Influence of Edge Effects on Single Event Upset Susceptibility of SOI SRAM, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 2015, Vol. 342, P. 286-291

6.        H. B. Wang, J. S. Bi, M. L. Li, L. Chen, R. Liu, Y. Q. Li, A. L. He, and G. Guo, An Area Efficient SEU-Tolerant Latch Design, IEEE Transactions on Nuclear Science, 2014, Vol. 61, No. 6, P. 3660 - 3666

7.        W. G. Bennet, N. C. Hooten, R. D. Schrimpf, R. A. Reed, M. H. Mendenhall, M. L. Alles, J. Bi, E. X. Zhang, D. Linten, M. Jurzak and A. Fantini, Single- and multiple-event induced unpsets in HfO2/Hf 1T1R RRAM, IEEE Transactions on Nuclear Science, 2014, Vol. 61, No. 4

8.        Bi Jin-Shun, Zeng Chuan-Bin, Gao Lin-Chun, Liu Gang, Luo Jia-Jun, and Han Zheng-Sheng, Estimation of pulsed laser induced single event transient in a partially-depleted silicon-on-insulator 0.18 μm MOSFET, Chinese Physics B, 2014, Vol. 23, No. 8

9.        Haibin Wang, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Rita Fung, Jinshun Bi, Single Event Resilient Dynamic Logic Designs, Journal of Electronic Testing: Theory and Applications, 2014,Vol. 30, No. 6

10.        Jinshun Bi, Zhengsheng Han, En Xia Zhang, Mike McCurdy, R. A. Reed, R. D. Schrimpf, D. M. Fleetwood, Michael L. Alles, Robert A. Weller, Dimitri Linten, Malgorzata Jurczak, and Andrea Fantini, The Impact of X-Ray and Proton Irradiation on HfO2/Hf-based Bipolar Resistive Memories, IEEE Transactions on Nuclear Science, 2013, Vol. 60, No. 6

11.        Jordan D Greenlee, Joshua C. Shank, James L. Compagnoni, M. Brooks Tellekamp, Enxia Zhang, Jinshun Bi, Daniel M. Fleetwood, Michael L. Alles, Ronald D. Schrimpf, and W. Alan Doolittle, Radiation effects on LiNbO2 memristor for neuromorphic computing applications, IEEE Transactions on Nuclear Science, 2013, Vol. 60, No. 6

12.        Jinshun Bi,Gang Liu,Jiajun Luo,Zhengsheng Han,Numerical simulation of single-event-transient effects on ultra-thin-body fully-depleted silicon-on-insulator transistor based on 22 nm process node,Acta Phys. Sin,2013,Vol. 62, No. 20

13.        Jinshun Bi,Chaohe Hai,Zhengsheng Han,Study on power characteristics of deep sub-micron SOI RF LDMOS, Acta Phys. Sin,2011,Vol. 60, No.1

EI journal papers:

1.        Jinshun Bi, Zhengsheng Han, Characteristics of HfO2/Hf-based Bipolar Resistive Memories, Chinese Journals of Semiconductors, 2015, Vol. 36, No. 6, P. 80-84

2.        Jinshun Bi,Zhengsheng Han,Study on Hf/HfO2 Bipolar Resistive Random-Access-Memory, Journal of Functional Materials and Devices,2014, Vol. 20, No. 5

3.        Bo Mei, Jinshun Bi, Duoli Li, Sinan Liu, and Zhengsheng Han, Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET, Chinese Journals of Semiconductors, 2012, Vol. 33, No.2, P. 024002-5

4.        Jianhui Bo, Jinshun Bi, Mengxin Liu, and Zhengsheng Han, A total dose radiation model for deep submicron PDSOI NMOS, Chinese Journals of Semiconductors, 2011, Vol. 32, No. 1, P. 014002-3

5.        Jianhui Bo, Jinshun Bi, Limei Song, and Zhengsheng Han, Short channel effect in deep submicron PDSOI nMOSFETs, Chinese Journals of Semiconductors, 2010, Vol. 31, No.1, P. 014002-3

6.        Jianhui Bo, Jinshun Bi, Linmao Xi, and Zhengsheng Han, Deep submicron PDSOI thermal resistance extraction, Chinese Journals of Semiconductors, 2010

7.        Wenbin Song, Jinshun Bi, and Zhengsheng Han, A novel SOI-DTMOS structure from circuit performance considerations, Chinese Journals of Semiconductors, 2009, Vo. 30, No.2, P. 024002-5

8.        Jinshun Bi, Limei Song, Chaohe Hai, and Zhengsheng Han, Back-gate effect of SOI LDMOSFETs, Chinese Journals of Semiconductors, 2008, Vol. 29, No. 11 P. 2148-2152

9.        Jinshun Bi, and Chaohe Hai, Off-state breakdown characteristics of PDSOI nMOSFETs, Chinese Journals of Semiconductors, 2007, Vol. 28, No. 1, P. 14-18

10.        Jinshun Bi, and Chaohe Hai, Study on the characteristics of SOI DTMOS with reverse schottky barriers, Chinese Journals of Semiconductors, 2006, Vol. 27, No.9, P. 1526-1530

11.        Jinshun Bi, Junfeng Wu, and Chaohe Hai, Simulation of a double-gate dynamic threshold voltage fully depleted silicon-on-insulator nMOSFET, Chinese Journals of Semiconductors, 2006, Vol. 27, No.1, P. 35-40

12.        Jinshun Bi,Chaohe Hai,A Study on Characteristics of PDSOI Round Gate nMOS with Body Tied to Source, Research & Progress of Solid State Electronics,2008,Vol. 28, No. 1

13.        Jinshun Bi,Chaohe Hai,Zhengsheng Han,Overview of SOI DTMOS (Dynamic-Threshold MOSFET),Chinese Journal of Electron Devices,2005,Vol. 28, No. 3

Core Chinese periodical Papers:

1.        Chi Wu,Jinshun Bi ,Rui Teng ,Bingqing Xie ,Zhengsheng Han ,Jiajun Luo,Gang Guo ,Jie Liu ,Overview of SEE modeling in complicated digital circuits,Microelectronics,2016, No. 1,P. 117-123

2.        Bingqing Xie,Jinshun Bi,Bo Li,Jiajun Luo,Overview of cryogenic characteristics in silicon-based devices and circuits,Microelectronics,2016

3.        Jinshun Bi,Shaoxu Jia,Zhengsheng Han,Jiajun Luo,The impacts of backend interconnects on SEE in ICs,Journal of Terahertz Science and Electronic Information Technology,2016,

4.        Shuo Guo, Jinshun Bi,Jiajun Luo,Zhengsheng Han,3D semiconductor device SEE simulation based on Geant4,Semiconductor Technology,2015,Vol. 40, No. 8, P. 592 – 595

5.        Jinhua Bao,Yinxue Lv,Bo Li,Chuanbin Zeng,Jinshun Bi,Jiajun Luo,Implementation of a PLL based on standard CMOS process,Electronics Engineering,2015

6.        Jinhua Bao,Bo Li,Chuanbin Zeng,Linchun Gao,Jinshun Bi,Jiajun Luo,PLL SEE analysis and hardening design,Semiconductor Technology,2015

7.        Shaoxu Jia,Jinshun Bi,Chuanbin Zeng,Zhengsheng Han,Geant4 simulation of contribution of nuclear reaction to single event upset,Nuclear Techniques,2012,No. 10

8.        Zihan Fan,Jinshun Bi,Jiajun Luo,A Study of Physics-basis SEU SPICE Model,Microelectronics & Computer,2011,No. 12

9.        Jinshun Bi,Zhengsheng Han,Chaohe Hai,Study on Temperature Characteristics of SOI DTMOS,Semiconductor Technology,2010,Vol. 35, No. 7, P. 661-663

10.        Jianhui Bo,Jinshun Bi,Limei Song,Zhengsheng Han,Hot Carrier Effect in Deep Submicron Radiation Hardened PDSOI nMOSFETs,Microelectronics,2010,Vol. 40, No. 3, P. 461-463

11.        Jinshun Bi,Zhengsheng Han,Chaohe Hai,Study on Body Delay of 130 nm PDSOI DTMOS,Semiconductor Technology,2010,Vol. 35, No. 9, P. 868-870

12.        Wenbin Song,Jinshun Bi,Zhengsheng Han,Novel Body-Contact Structure Technology for Partially Depleted SOI MOSFET,Semiconductor Technology,2008,Vol. 33, No.11, P. 968-971

13.        Xuemei Fan,Jinshun Bi,Mengxin Liu, Huan Du,An Overview of Low-Frequency Noise in PD SOI MOSFET,Microelectronics,2008,38(6)

14.        Jinshun Bi,Chaohe Hai,Study on 0.8μm PDSOI CMOS Devices and Ring Oscillators,Semiconductor Technology,2007,Vol. 32, No. 6, P. 490-493

International Conference Papers:

1.        R. Gao, Z. Ji, S. M. Hatta, J. F. Zhang, J. Franco, B. Kaczer, W. Zhang, M. Duan, S. De Gendt, D. Linten, G. Groeseneken, J. Bi and M. Liu, Predictive As-grown-Generation (A-G) model for BTI-induced device/circuit level variations in nanoscale technology nodes, 2016 IEEE International Electron Devices Meeting (IEDM)

2.        Jinshun Bi, Ming Liu, Zhengsheng Han, The Body Bias Effects on the Single-Event-Transient of Silicon-On-Insulator CMOS Technology, International Conference on Radiation and Applications in Various Fields of Research, 2016, Serbia

3.        Jinshun Bi, Jin Li, Langlong Ji, Hongyang Hu, and Ming Liu, The impacts of total ionizing dose irradiation on NOR Flash memory, IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, China

4.        Kai Xi, Jinshun Bi, Ming Liu, Jie Liu, Yan Wang, and Mingdong Hou, Sensitivity of Proton Single Event Effect Simulation Tool to Variation of Input Parameters, IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, China

5.        Haohao Zhang, Jinshun Bi, Yuan Duan, Yannan Xu, and Ming Liu, Proton Irradiation Effects and Annealing Behaviors of 16Mb Magneto-resistive Random Access Memory(MRAM), IEEE 13th International Conference on Solid-State and Integrated Circuit Technology, 2016, China

6.        Jinshun Bi, Li Chen, Jin Li, Lanlong Ji, Hongyang Hu, Ming Liu, Total Ionizing Dose and Heavy Ion Effects of 4Mb Serial-Peripheral-Interface(SPI) NOR Flash Memory, IEEE Radiation Effects Data Workshop, 2016, USA

7.        Haohao Zhang, Jinshun Bi, Li Chen, in Li, Lanlong Ji, Hongyang Hu, Le Hao, Ming Liu, Total Ionizing Dose Effects and Annealing behaviors of a Commercial 16 Mb Magneto-resistive Random Access Memory (MRAM), IEEE Radiation Effects Data Workshop, 2016, USA

8.        Yan Wang, Yang Li, Qi Liu, Jinshun Bi, Jing Liu, Haitao Sun, Hangbing Lv, Shibing Long, Kai Xi, Ming Liu, The Heavy Ion Radiation Effects on the Pt/HfO2/Ti Resistive Switching Memory, IEEE Radiation and its Effects on Components and Systems, 2016, German

9.        Jinshun Bi, Jianhui Bu, Ming Liu, Zhengsheng Han, The impact of drain bias on laser-induced single event transient in a 0.18μm PDSOI transistor, ICREED, 2015, China

10.        Bo Li, Jinshun Bi, Jia-Jun Luo, Zheng-Sheng Han, Xue-Fang Lin-Shi, Bruno Allard, An SEE Prognostic Cell Embedded Rad-hard Digital Controller for Next Generation DC-DC Converter in Space, ICREED, 2015, China

11.        Jinshun Bi, Li Chen, Zhengsheng Han,Yan Wang, Ming Liu, Body Bias Effects on the Single-Event-Transient Response of PDSOI Devices, IEEE Radiation and its Effects on Components and Systems, 2015, Russia

12.        Yan Wang, Jinshun Bi, Jing Liu, Qi Liu, Hangbing Lv, Shibing Long, Ming Liu, The TID Effects of RRAM based Oxide Material, IEEE Radiation and its Effects on Components and Systems, 2015, Russia

13.        Xuefang Lin-Shi, Bruno Allard, Jinshun Bi, Bo Li, A Stability Analysis Method for DC/DC Converters, The 6th International Conference on Electrical and Control Engineering, 2015, China

14.        Wenbin Song, Jinshun Bi, A Method of Extracting the Parameters of SOI MOS Device based on BSIMSOI3 Model, 2nd International Conference on Communication Technology, 2015

15.        Jinshun Bi, RRAM: Potential Candidate for Space Electronics?, 1st China-Japan-Korea RRAM and Functional Oxide Workshop, 2014, China

16.        Jinshun Bi, Chuanbin Zeng, Linchun Gao, Duoli Li, Gang Liu, Jiajun Luo, and Zhengshen Han, Effects of Contact Materials and Geometry on Pulsed-Laser Single Event Transient Testing, IEEE 27th International Conference on Microelectronic Test Structures, 2014, Italy

17.        Jinshun Bi,, Zhengsheng Han, Mitigation of Soft Errors in Resistive Switching Random-Access-Memories, IEEE International Conference on Electron Devices and Solid-State Circuits, 2014, China

18.        Jinshun Bi, Bo Li, Zhengsheng Han, Jiajun Luo, Li Chen, and Xuefang Lin-Shi, 3D TCAD Simulation of Single-Event-Effect in N-Channel Transistor based on Deep Sub-Micron Fully-Depleted Silicon-On-Insulator Technology, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

19.        Shuo Guo, Jinshun Bi, Jiajun Luo, Zhengsheng Han, 3-D Geant4 Simulation of Deep Sub-Micron SOI SRAM Irradiated by Proton, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

20.        Bo Li, Jinshun Bi, Zhengsheng Han, Jiajun Luo, Xuefang Lin-Shi, Bruno Allard, and Li Chen, A Digital Direct Controller for Buck Converter, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

21.        Xuefang Lin-Shi, Bruno Allard, Jinshun Bi, and Bo Li, Stability Analysis for Integrated DC/DC Converters, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

22.        Xing Zhao, Bo Mei, Jinshun Bi, Zhongshan Zheng, Linchun Gao, Chuanbin Zeng, Jiajun Luo, Fang Yu, and Zhengsheng Han, Single Event Transient in PDSOI CMOS Inverter Chain Irradiated by Pulsed Laser, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

23.        Kai Zhao, Xing Zhao, Jiantou Gao, Jinshun Bi, Jiajun Luo, Fang Yu, and Zhongli Liu, DSOI FET – A Novel TID Tolerant SOI Transistor, IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, 2014, China

24.        Jinshun Bi, Chuanbin Zeng, Linchun Gao, Duoli Li, Gang Liu, Jiajun Luo, Zhengsheng Han, R. A. Reed, R. D. Schrimpf, and D. Fleetwood, Estimation of pulsed laser induced single event transient in a PDSOI 0.18μm single MOSFET, The 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications, 2012, Japan

25.        Jinshun Bi, Zhengsheng Han, R. A. Reed, R. D. Schrimpf, and D. M. Fleetwood, Neutron-induced single-event-transient effects in ultrathin-body fully-depleted silicon-on-insulator MOSFETs, IEEE International Reliability Physics Symposium, 2013, USA

26.        Jinshun Bi, Zhengsheng Han, En Xia Zhang, Mike McCurdy, R. A. Reed, R. D. Schrimpf, D. M. Fleetwood, Michael L. Alles, Robert A. Weller, Dimitri Linten, Malgorzata Jurczak, and Andrea Fantini, Total-dose response of HfO2/Hf-based bipolar resistive memories, IEEE Nuclear and Space Radiation Effects Conference(NSREC), 2013, USA

27.        Jordan D Greenlee, Joshua C. Shank, James L. Compagnoni, M. Brooks Tellekamp, Enxia Zhang, Jinshun Bi, Daniel M. Fleetwood, Michael L. Alles, Ronald D. Schrimpf, and W. Alan Doolittle, Radiation effects on LiNbO2 memristor for neuromorphic computing applications, IEEE Nuclear and Space Radiation Effects Conference(NSREC), 2013, USA

28.        William G. Bennett, Nicholas C. Hooten, Ronald D. Schrimpf, Jinshun Bi, Mike L. Alles, Robert A. Reed, Dimitri Linten, Malgorzata Jurczak, and Andrea Fantini, Single event induced upsets in HfO2/Hf 1T1R RRAM, Radiation Effects on Components and Systems(RADECS), 2013, UK

29.        Jinshun Bi, Gang Liu, Jianjun Luo , and Zhengsheng Han, High reliable silicon-on-insulator CMOS technology aimed at lunar and deep space exploration, 1st Beijing International Forum on Lunar and Deep-space Exploration, 2013, China

30.        Jianhui Bo, Jinshun Bi, Xianjun Ma, Jiajun Luo, Zhengsheng Han, and Haogang Cai, A compact model for the STI y-stress effect on deep submicron PDSOI MOSFETs, International Conference on Solid-State and Integrated-Circuit Technology, 2012, China

31.        Jinshun Bi, Jianhui Bo, and Zhengsheng Han, Extraction method for thermal resistance in deep submicron PDSOI MOSFETs, International Conference on Microelectronics and Nanotechnology, 2010, Netherlands

32.        Jinshun Bi, and Chaohe Hai, The PDSOI accumulation-mode dynamic threshold pMOS with reversed schottky barrier, International Conference on Solid-State and Integrated-Circuit Technology, 2007, China

Chinese Conference Papers:

1.        Jinshun Bi,4M Flash memory SEE based on heavy ion micro-beam technique,2th Chinese Workshop on Radiation Physics,2016

2.        Chi Wu,Jinshun Bi,Zhengsheng Han,Jiajun Luo,SET generation and propagation based on 0.13μm PDSOI process,12th Chinese Workshop on Radiation Electronics and EMP,2015

3.        Jinshun Bi,Shaoxu Jia,Zhengsheng Han,Jiajun Luo,The impacts of backend interconnects on SEE in ICs,12th Chinese Workshop on Radiation Electronics and EMP,2015

4.        Xing Zhao,Jinshun Bi,Zhongshan Zheng,Kai Zhao,Fang Yu,Jiajun Luo,Zhengsheng Han,0.2μm FDSOI NMOSFET back-gate effects and TID Responses,12th Chinese Workshop on Radiation Electronics and EMP,2015

5.        Jinhua Bao,Chuanbin Zeng, Bo Li,Linchun Gao,Hainan Liu,Jinshun Bi,Jiajun Luo,Laser experiments on Asynchronous TSPC dividers,12th Chinese Workshop on Radiation Electronics and EMP,2015

6.        Haohao Zhang,Jinshun Bi, Ming Liu,Overview of MRAM Radiation Effects and Hardening Techniques,7th Workshop on CAS posdoc, 2015

7.        Jinshun Bi,Jiajun Luo,Zhengsheng Han,Overview of laser SEE systems and experimental methods,Chinese Radiation Physics Symposium,2014

8.        Linchun Gao,Na Yang,Chuanbin Zeng,Jinshun Bi,Gang Liu,Jiajun Luo,Zhengsheng Han,Influence factors of front-side injected laser on SEE Test,Chinese Radiation Physics Symposium,2014

9.        Shaoxu Jia,Jinshun Bi,Gang Liu,Jiajun Luo,Zhengsheng Han, Semiconductor SEU simulations based on Geant4,Chinese Aeronautics Society Deep Space Exploration Conference,2013

10.        Xiaohui Su,Jinshun Bi,Gang Liu,Jiajun Luo,Zhengsheng Han,Study on Radiation-Induced SET Pulse Width Measurement Circuit, Chinese Aeronautics Society Deep Space Exploration Conference,2013

11.        Jinshun Bi,Chuanbin Zeng,Gang Liu,Jiajun Luo,Zhengsheng Han,Cryogenic Radiation Hard IC Design Methodologies aiming at Deep Space Exploration,Chinese Aeronautics Society Deep Space Exploration Conference,2011

12.        Jinshun Bi,Zihan Fan,Chuanbin Zeng,Jiajun Luo,Zhengsheng Han,PDSOI SEU SPICE Model,17th Workshop on Semiconductor circuits and Silicon Material,2011

13.        Jian Tian,Jinshun Bi,Jiajun Luo,Zhengsheng Han,Damage Mechanisms on Thin Gate Oxide,17th Workshop on Semiconductor circuits and Silicon Material,2011

14.        Jianhui Bo,Jinshun Bi,Yinxue Lv,Jiajun Luo,Zhengsheng Han,Deep sub-micron PDSOI nMOSFETs HCI lifetime,17th Workshop on Semiconductor circuits and Silicon Material,2011

15.        Chuanbin Zeng,Jinshun Bi,Yibo Jiang,Jiajun Luo,Zhengsheng Han,SCR Structures of PDSOI ESD Protection,17th Workshop on Semiconductor circuits and Silicon Material,2011

16.        Jianhui Bo,Jinshun Bi,Mengxin Liu,Jiajun Luo,Zhengsheng Han,SOI Device TID Model,11th Anti-Radiation and EMP Conference,2011

17.        Jinshun Bi,Chaohe Hai,Study on Radiation Hard SOI SRAM,7th SOI Technology Conference,2007

18.        Jinshun Bi,Chaohe Hai,Low Voltage Low Power Full Adder based on PDSOI DTMOS,5th SOI Technology Conference,2005

Honour:

2007 Chinese Academy of Sciences Dean Reward

Patents Application:

Granted Patents:

1.        Patent Name:Test equipment and method for SOI MOSFET flicker noise

Appl.No.:CN201410031166.X

Authorization Date:2016.07.06

Inventors:Shuzhen Li, Jianhui Bo, Jinshun Bi, Chuanbin Zeng, Jiajun Luo, Zhengsheng Han

2.        Patent Name:Test equipment and test method for SOI MOS component flashing noise

Appl.No.:CN:201410031166:A

Authorization Date:2016.07.06

Inventors:Shuzhen Li, Jianhui Bo, Jinshun Bi, Chuanbin Zeng, Jiajun Luo, Zhengsheng Han

3.        Patent Name:CMOS circuits to mitigate SET pulse

Appl.No.:CN201310438775.2

Authorization Date:2016.01.27

Inventors:Xiaohui Su, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Le Hao

4.        Patent Name:CMOS circuits to mitigate SET pulse

Appl.No.:CN201310439034.6

Authorization Date:2016.03.02

Inventors: Xiaohui Su, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Le Hao

5.        Patent Name:CMOS circuits to mitigate SET pulse

Appl.No.:CN201310438818.7

Authorization Date:2016.03.02

Inventors:Xiaohui Su, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Le Hao

6.        Patent Name:SOI MOSFET thermal resistance extraction method

Appl.No.:CN201310339890.4

Authorization Date:2016.03.23

Inventors:Jianhui Bo, Ying Li, Jinshun Bi, Shunzhen Li, Jiajun Luo, Zhengsheng Han

7.        Patent Name: Modeling method for SOI H-gate MOS devices

Appl.No.:CN201210536882.4

Authorization Date:2015.05.27

Inventors:Jianhui Bo, Jinshun Bi, Jiajun Luo, Zhengsheng Han

8.        Patent Name:Modeling method for SOI MOS devices

Appl.No.:CN201210248270.5

Authorization Date:2014.10.15

Inventors:Jianhui Bo, Jinshun Bi, Jiajun Luo, Zhengsheng Han

9.        Patent Name:PN junction depth calculation method

Appl.No.:CN201210212571.2

Authorization Date:2014.07.02

Inventors:Jianhui Bo, Jinshun Bi, Jiajun Luo, Zhengsheng Han

10.        Patent Name:MOS devices modeling method

Appl.No.:CN201210212516.3

Authorization Date:2014.11.26

Inventors:Jianhui Bo, Jinshun Bi, Jiajun Luo, Zhengsheng Han

11.        Patent Name:SOI MOS transistor

Appl.No.:CN201210154443.7

Authorization Date:2014.12.17

Inventors:Ying Li, Jinshun Bi, Jiajun Luo, Zhengsheng Han

12.        Patent Name:MOS devices modeling method

Appl.No.:CN201210123082.X

Authorization Date:2015.02.18

Inventors:Jianhui Bo, Jinshun Bi, Bo Mei, Jiajun Luo, Zhengsheng Han

13.        Patent Name:SET pulse width measurement circuit

Appl.No.:CN201210080931.8

Authorization Date:2014.08.20

Inventors:Xiaohui Su, Jinshun Bi, Jiajun Luo

14.        Patent Name:SEE laser emulation system

Appl.No.:CN201110459433.X

Authorization Date:2014.01.29

Inventors:Chuanbin Zeng, Linchun Gao, Jinshun Bi, Jiajun Luo, Zhengsheng Han

15.        Patent Name:Radiation-Hard SOI structure and fabrication method

Appl.No.:CN201110418323.9

Authorization Date:2015.02.18

Inventors:Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye

16.        Patent Name:SOI structure anti-radiation performance improvement method

Appl.No.:CN201110418276.8

Authorization Date:2015.06.24

Inventors:Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye

17.        Patent Name:SCR structure to tune holding voltage

Appl.No.:CN201110332265.8

Authorization Date:2013.04.24

Inventors:Chuanbin Zeng, Jinshun Bi, Duoli Li, Jiajun Luo, Zhengsheng Han

18.        Patent Name:SCR structure for ESD protection

Appl.No.:CN201120417128.X

Authorization Date:2012.08.15

Inventors:Chuanbin Zeng, Jinshun Bi, Duoli Li, Jiajun Luo, Zhengsheng Han

19.        Patent Name:SET pulse width measurement circuit

Appl.No.:CN201110319780.2

Authorization Date:2015.08.05

Inventors:Xiaohui Su, Jinshun Bi

20.        Patent Name:Vacuum radiation equipment with temperature and input-gas controlled

Appl.No.:CN201110252532.0

Authorization Date:2015.07.08

Inventors:Chuanbin Zeng, Jinshun Bi, Gang Liu, Jiajun Luo, Zhengsheng Han

21.        Patent Name:Storage cell test circuit and test method

Appl.No.:CN201110208077.4

Authorization Date:2015.06.03

Inventors:Yiqi Wang, Zhengsheng Han, Fazhan Zhao, Mengxin Liu, Jinshun Bi

22.        Patent Name:SOI diode structure and fabrication method

Appl.No.:CN201110183539.1

Authorization Date:2014.10.15

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

23.        Patent Name:Batched MOS device layout design method

Appl.No.:CN201110160075.2

Authorization Date:2015.12.02

Inventors:Ying Li, Jinshun Bi

24.        Patent Name:SET pulse width measurement circuit

Appl.No.:CN201110152231.0

Authorization Date:2014.12.03

Inventors:Xiaohui Su, Jinshun Bi

25.        Patent Name:SOI RF LDMOS transistor structure

Appl.No.:CN201110007880.1

Authorization Date:2014.10.22

Inventors:Mengxin Liu, Jinshun Bi, Gang Liu, Jiajun Luo, Zhengsheng Han

26.        Patent Name:SOI NMOS TID modeling method

Appl.No.:CN201010251985.7

Authorization Date:2014.04.02

Inventors:Jianhui Bo, Jinshun Bi, Zhengsheng Han

27.        Patent Name:Modeling method for SOI body resistance

Appl.No.:CN201010217274.8

Authorization Date:2014.05.14

Inventors:Jianhui Bo, Jinshun Bi, Zhengsheng Han

28.        Patent Name:Prediction method for SOI devices HCI lifetime

Appl.No.:CN201010157559.7

Authorization Date:2013.08.07

Inventors:Jianhui Bo, Jinshun Bi, Maolin Xi, Zhengsheng Han

29.        Patent Name:CMOS radiation-hard IC

Appl.No.:CN200910244519.3

Authorization Date:2012.10.03

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

30.        Patent Name:SEE radiation-hard CMOS IC

Appl.No.:CN200910244523.X

Authorization Date:2012.10.17

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

31.        Patent Name:SOI RF LDMOS device and implantation method

Appl.No.:CN200910236718.X

Authorization Date:2012.11.21

Inventors:Mengxin Liu, Lei Chen, Jinshun Bi, Gang Liu, Zhengsheng Han

32.        Patent Name:Equipment and test method for transistor measurement

Appl.No.:CN200910308495.3

Authorization Date:2012.08.01

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

33.        Patent Name:SOI device and fabrication method

Appl.No.:CN200910305117.X

Authorization Date:2011.04.06

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

34.        Patent Name:CMOS circuit SET modeling method

Appl.No.:CN200910089598.5

Authorization Date:2012.10.03

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

35.        Patent Name:Method to fabricate PDSOI body contact

Appl.No.:CN200810116043.0

Authorization Date:2012.03.21

Inventors:Wenbin Song, Jinshun Bi, Zhengsheng Han

36.        Patent Name:H-gate RF SOI LDMOS

Appl.No.:CN200810057936.2

Authorization Date:2010.07.28

Inventors:Mengxin Liu, Jinshun Bi, Xuemei Fan, Chaorong Zhao, Zhengsheng Han, Gang Liu

37.        Patent Name:RF SOI LDMOS with compact body contacts

Appl.No.:CN200810057921.6

Authorization Date:2010.11.03

Inventors:Mengxin Liu, Jinshun Bi, Xuemei Fan, Chaorong Zhao, Zhengsheng Han, Gang Liu

38.        Patent Name:SOI body-contacted device fabrication method with low extension capacitance

Appl.No.:CN200610112701.X

Authorization Date:2009.04.22

Inventors:Jinshun Bi, Zhengsheng Han

Patents Pending:

39.        Patent Name:Control method for DC-AC buck converter

Appl.No.:CN201510355880.9

Appl. Date:2015.06.24

Inventors:Bingqing Xie, Bo Li, Jinshun Bi, Jiajun Luo, Jianhui Bo

40.        Patent Name:Control method for DC-DC buck converter

Appl.No.:CN201410663373.7

Appl. Date:2014.11.19

Inventors:Bo Li, Jinshun Bi, Hainan Liu, Zhengsheng Han, Jiajun Luo, Gang Liu

41.        Patent Name: DPWM setup for Switch power digital controller

Appl.No.:CN201410665987.9

Appl. Date:2014.11.19

Inventors:Bo Li, Jinshun Bi, Hainan Liu, Zhengsheng Han, Jiajun Luo, Gang Liu

42.        Patent Name:SET pulse magnitude measurement circuit

Appl.No.:CN201410209130.6

Appl. Date:2014.05.16

Inventors:Xiaohui Su, Jiajun Luo, Le Hao, Jinshun Bi, Xinxin Li, Haitao Zhao

43.        Patent Name:Anti-SET CMOS circuit

Appl.No.:CN201310449608.8

Appl. Date:2013.09.24

Inventors:Xiaohui Su, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Le Hao

44.        Patent Name:NMOS and PMOS device structures and design method

Appl.No.:CN201310098874.0

Appl. Date:2013.03.26

Inventors:Jianhui Bo, Jinshun Bi, Jiajun Luo, Zhengsheng Han

45.        Patent Name:SOI MOS transistor

Appl.No.:CN201210155387.9

Appl. Date:2012.05.18

Inventors:Ying Li, Jinshun Bi, Jiajun Luo, Zhengsheng Han

46.        Patent Name:SOI MOS transistor

Appl.No.:CN201210155009.0

Appl. Date:2012.05.17

Inventors:Ying Li, Jinshun Bi, Jiajun Luo, Zhengsheng Han

47.        Patent Name:Semiconductor structure fabrication method

Appl.No.:CN201210118939.9

Appl. Date:2012.04.20

Inventors:Jinshun Bi, Jiajun Luo, Zhengsheng Han

48.        Patent Name:Single event transient current pulse detection method

Appl.No.:CN201110457845.X

Appl. Date:2011.12.30

Inventors:Bo Mei, Jinshun Bi, Zhengsheng Han, Jiajun Luo

49.        Patent Name:Single event transient current pulse detection system

Appl.No.:CN201110457712.2

Appl. Date:2011.12.30

Inventors:Bo Mei, Jinshun Bi, Zhengsheng Han, Jiajun Luo

50.        Patent Name:MOS transistor capacitor

Appl.No.:CN201110309971.0

Appl. Date:2011.10.13

Inventors:Yiqi Wang, Zhengsheng Han, Fazhan Zhao, Mengxin Liu, Jinshun Bi

51.        Patent Name:FET transistor and fabrication method

Appl.No.:CN201110285830.X

Appl. Date:2011.09.23

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

52.        Patent Name:Method and setup to simulate pulse current

Appl.No.:CN201110243696.7

Appl. Date:2011.08.24

Inventors:Ying Li, Jinshun Bi, Jiajun Luo, Zhengsheng Han

53.        Patent Name:Circuit radiation performance simulation method and setup

Appl.No.:CN201110226452.8

Appl. Date:2011.08.09

Inventors:Jianhui Bo, Jinshun Bi, Zhengsheng Han, Jiajun Luo

54.        Patent Name:SOI-NMOS back-gate threshold voltage tuning method

Appl.No.:CN201110209296.4

Appl. Date:2011.07.25

Inventors:Bo Mei, Jinshun Bi, Zhengsheng Han

55.        Patent Name:Method to improve SOI-PMOS back-gate threshold voltage

Appl.No.:CN201110209346.9

Appl. Date:2011.07.25

Inventors:Bo Mei, Jinshun Bi, Zhengsheng Han

56.        Patent Name:Thermal resistance extraction method for SOI FET transistor

Appl.No.:CN201110187366.0

Appl. Date:2011.07.05

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo

57.        Patent Name:Simulation analysis circuit for SEU in PDSOI devices

Appl.No.:CN201010566061.6

Appl. Date:2010.11.29

Inventors:Zihan Fan, Jinshun Bi, Jiajun Luo

58.        Patent Name:TID radiation model extraction method for semiconductor devices

Appl.No.:CN201010145101.X

Appl. Date:2010.04.09

Inventors:Jianhui Bo, Jinshun Bi, Zhengsheng Han

59.        Patent Name:Model extraction method for semiconductor devices

Appl.No.:CN201010145308.7

Appl. Date:2010.04.09

Inventors: Jianhui Bo, Jinshun Bi, Zhengsheng Han

60.        Patent Name:Optical system and test method to characterize the Si/SiO2 interface

Appl.No.:CN200810224907.0

Appl. Date:2008.10.24

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han

61.        Patent Name:Dual-gate FDSOI CMOS device and fabrication method

Appl.No.:CN200710063371.4

Appl. Date:2007.01.10

Inventors:Chaohe Hai, Jinshun Bi, Haifeng Sun, Zhengsheng Han, Lixin Zhao

62.        Patent Name:Fabrication method for source-body ohmic-contacted SOI transistor

Appl.No.:CN200610113722.3

Appl. Date:2006.10.13

Inventors:Jinshun Bi, Chaohe Hai

63.        Patent Name:High breakdown voltage SOI device and fabrication method

Appl.No.:CN200610104117.X

Appl. Date:2006.07.31

Inventors:Jinshun Bi, Junfeng Wu, Chaohe Hai, Zhengsheng Han

64.        Patent Name:SOI DTMOS with gate-body reverse biased schottcky junction

Appl.No.:CN200610083997.7

Appl. Date:2006.06.16

Inventors:Jinshun Bi, Chaohe Hai, Zhengsheng Han

Projects and Subjects Participated

1.        Youth Innovation Promotion, CAS, 2014/01-2017/12, 400k RMB, PI;

2.        Key project of Chinese National Science Foundation, 61634008, Basic research on radiation effects and hardening techniques of advanced non-volatile memory (NVM), 2017/01-2021/12, 3.28M RMB, PI;

3.        General program of Chinese National Science Foundation, 61176095, Mechanisms of radiation-induced damages on deep-sub-micron SOI integrated devices aiming at space application, 2012/01-2015/12, 770k RMB, PI;

4.        Key project of Chinese National Science Foundation, 11179003, Single-event effects and ground-based experimental methodologies for space radiation environment, 2012/01-2015/12, 2.5M RMB, Co-PI;

5.        National Science and Technology Major Project, 10ZX02305-008, Product design and verification on advanced process platform, 2009/01/01-2015/06/30, 4.98M RMB, Co-PI;

6.        Chinese National Science Funds for Creative Research Groups of China, 61521064, Basic research on emerging microelectronics devices integration, 2016/01-2018/12, 6M RMB, Co-PI;

7.        Funds for International Cooperation, The Chinese Academy of Sciences, 172511KYSB20150006, Flash memory radiation effects simulations, 2015/09-2018/08, 900k RMB, Co-PI;

8.        Sino-French "Cai Yuanpei" exchanges and cooperation projects, Digital feedback control loop of SOI-based DC-DC converters, 2015/05-2017/05, PI;

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