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Scientists Develop Gate-All-Around Silicon Nanowire Transistors with Channel-last Process on Bulk Si Substrate
Author: Dept.10 MA Xiaolong;Translate by Dan
Update time: 2015-07-21
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The Gate-All-Around (GAA) Silicon Nanowire Transistors (SNWT) has attracted considerable attention during the last decades as a promising candidate to overcome the scaling issues of MOSFETs at the roadmap of integration circuit process technology. For the purpose of applying the SNWT structures into the fabrication process flow of conventional bulk-silicon (Si) FinFETs for mass production, the fabrication technologies of GAA-SNWTs are necessary to be compatible with current state-of-the-art integration technology. However, the traditional approach to fabricate GAA-SNWTs is to form and release the NW channels in the initial step of the transistor’s fabrication and it causes a series of integration challenges.

Recently, scientists from Integrated Circuit Advanced Process Center of the Institute of Microelectronics (IME) of Chinese Academy of Sciences developed a novel technology of Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology . Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conven-tional bulk-Si FinFET. The GAA-SNWT with the NCL approach is successfully fabricated with the excellent electrical characteristics in the integration process.

Figure 1. The Fabrication Method of GAA-SNWT with NCL Process Based on the Integration Fow of Conventional Bulk-Si FinFETs.

Figure 2. (a) The IDS-VGS Curves of the Fabricated N-type GAA-SNWT by NCL Process with LG ¼ 100 nm; (b) The Cross-Sectional Image of the NW Channel with Multi-Layered HKMG Stacks.

The fabricated n-type GAA-SNWT by NCL process demonstrated excellent SS (< 65 mV/V) and DIBL (< 25 mV/V) as well as off-current (< 2 Â 10À10 A/µm) parameters after H2 baking and gate interface oxidation optimization on NW channels in gate-last process. The new technology provides a promising approach for the integration of nanowire technology into the industrial FinFET flow for mass production in next generations.

This work was supported by “16/14nm Basic Technology Research” of national 02 IC projects in China (No. 2013ZX02303). The study has been published in IEICE Electronics Express.MA X, YIN H, HONG P. Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate [J]. IEICE Electronics Express, 2015, 12(7): 20150094.


Researcher ZHAO Chao

E-mail: zhaochao@ime.ac.cn

Website of Dept.http://english.ime.cas.cn/Research/ResearchDivisions/LAB10/


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