Near / sub threshold technique is the most cutting-edge and effective ultra-low-power technology in recent years. It can optimize dynamic power consumption and static power consumption simultaneously, as shown in Figure 1. Recently, researchers in the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS) apply near / sub threshold technique to chip manufacturing. The intelligent power / clock management and ultra-low leakage circuit design are used in the chip process. Through the comprehensive application of near threshold transistor characteristics, process deviation analysis, noise margin optimization and so on, the IP library in the chip can work stably under 0.5V. Dynamic power consumption decreased by 19 times. Static power consumption decreased by 7 times. The chip supports multiple modes of operation, including Active, Low Power Active, Idle, Standby, Back Up, Off and so on. It can consume minimum energy by using the simplest logic in different application scenarios. In order to reduce the leakage power consumption in standby mode, the chip uses the technology of ultra-low leakage memory, ultra-low leakage logic design, fine power and Input- Output (IO) management strategy and so on. The minimum mode leakage power consumption is only 25nA, achieving the leading level of the current ultra-low power processor chip.
This research was supported by the National High Technology Research and Development Program of China (863 program), Pilot Project of the Chinese Academy of Sciences and the National Natural Science Foundation of China.
Figure 1: Advantages of Low-Voltage Technology (Left) and Low-Voltage Effect Diagram (Right)
(Image by IMECAS)
Researcher YAN Yuepeng
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