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Maskmakers Struggle to Find the ROI on EUV Masks
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Update time: 2010-03-02
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Like others with a stake in EUV lithography development, maskmakers are being asked to contribute money to a Sematech effort to close the funding gap in mask inspection development. It's a tough question, however, given the low probability of a return on that investment anywhere in the near future.
Aaron Hand, Editor-in-Chief -- Semiconductor International, 2/24/2010

The semiconductor industry has invested heavily in the development of EUV lithography, and most have accepted it as the technology that will carry circuit patterning beyond 22 nm half-pitch. But when proponents point to the technology's cost-effectiveness, their cost estimates too often disregard realistic numbers for the mask component of the equation.
Complaints from other camps (including the maskmakers themselves) contend that EUV mask costs are grossly underestimated, and in many cases are largely ignored. Even in a panel discussion Monday night at SPIE Advanced Lithography that was specifically focused on masks, TSMC's Tony Yen ultimately had to concede that the chart he put up on the screen showing EUV as the winner on the cost front did not actually factor in the mask costs.
In a sea of EUV lithography investments, the mask infrastructure, in fact, has been woefully underfunded. Over the past year or so, it has been concern over funding for mask inspection, in particular, that has garnered considerable attention. And coming away from the latest EUV Lithography Symposium, held in Prague, Czech Republic, in November, the program's steering committee moved mask infrastructure to the top of the critical list for EUVL readiness.
Although source power remains a critical challenge for getting EUV lithography to high-volume production, source suppliers have been funding development in this area, and scanner manufacturers have delivered the tools that help to confirm ultimate source readiness. Mask inspection, however, has not seen a similar commitment, and questions still remain about how the desperately needed infrastructure will be funded.
Sematech vowed earlier last year to do something about it. The research organization has since been gathering momentum, and has begun looking for the financial support needed from the key industry stakeholders. Sematech announced last week the forming of the EUVL Mask Infrastructure (EMI) consortium, noting that it had "strong interest" from six semiconductor industry entities.

Toppan Photomasks, which has already been making EUV masks for the industry, is one company that has been approached by Sematech, and is thinking hard about the feasibility of investment, according to Franklin Kalk, the maskmaker's CTO. No money has been exchanged yet, Kalk said this week, but Toppan has been in serious talks with Sematech about the issues involved.
But maskmakers have concerns about their likely return on investment (ROI), which is a dodgy equation when considering the relatively low number of chipmakers that will likely be able to afford to play in the EUV space. The subject came up repeatedly in the Monday night Bacus panel designed to explore mask-related concerns in all four remaining next-generation lithography (NGL) candidates — EUV, nanoimprint, double patterning and direct-write e-beam. Photronics' Bryan Kasprowicz, who moderated the discussion along with Kalk, also expressed concern over the troubling ROI numbers: "For us, it's not cost-effective."
Intel's Yan Borodovsky spoke on Sunday about the continued use of 193 nm immersion lithography through the 11 nm node. Nonetheless, EUV lithography is a technology that appeals to big chip manufacturers like Intel and Samsung partly because it runs high volumes of wafers to help amortize the mask costs.
Even foundry leader TSMC turned heads this week with an announcement that it would take delivery of an NXE:3100 EUV scanner from ASML in its Fab 12 GigaFab — this directly on the heels of an announcement of its latest achievements with e-beam tool developer Mapper, and ongoing support of the competing technology. Yen said Monday night that, as a member of IMEC, TSMC has been printing wafers on the ASML alpha demo tool (ADT) at IMEC for more than a year, and will continue to do so until it takes delivery of its own EUV tool.
Yen also made mention that TSMC has been producing EUV masks in-house — a key consideration for merchant maskmakers as they look at the potential upside of investing in EUV maskmaking capabilities. Kalk noted in a separate conversation that many of the chipmakers likely to participate in the first wave of EUV production have their own captive mask shops, making the merchant maskmakers wonder even more when they might see a return on their investment. The question, in part, is when the second wave of chipmakers is likely to start buying EUV masks, Kalk said. "If it's going to take seven years for payback, that's a hard sell."

Another concern even in the long run is the expected volumes for EUV masks, given the inevitable consolidation in the market. Right now, Toppan Photomasks is production one or two EUV masks a month — the most of any maskmaker, according to Kalk. Once EUV reaches volume production, that number could reach one mask a day — not anywhere close to the number of leading-edge phase-shift masks produced today. Given the considerable investment that will be needed to acquire AIMS tools and blank and patterned inspection tools, the cost per mask is likely to be very high, Kalk said.

As a foundry, GlobalFoundries is looking at runs of ~1000 wafers/reticle, in contrast to the 50,000 wafers/reticle AMD was producing. "The relative mask cost is huge," noted GlobalFoundries' Paul Ackmann during the panel discussion. Given that GlobalFoundries may not have a captive mask shop, Ackmann was asked what his confidence level is in the ability of merchant maskmakers to supply the EUV masks. He expressed concern that they would be able to afford that business, given a likely equation of five masks a week. "You do the math," he said. "You can't run enough wafers."

Sematech's EMI consortium is designed to solve the funding gaps for the EUV mask infrastructure. Bryan Rice, director of lithography at Sematech, estimates that $70M will be needed to develop mask defect review by 2013. Some $5M-$10M will be needed to develop an optical mask blank inspection tool for 22 nm technology by 2011, and an additional $50M for an actinic solution for the 16 nm node by perhaps 2013. And mask actinic patterned inspection will cost $30M for a research tool and another $150M for a development tool by around 2015. Carl Zeiss is confident that it can develop the AIMS tool within a three-year timeframe if the EMI consortium can come up with the money, according to Oliver Kienzle, managing director of the Carl Zeiss Semiconductor Metrology Systems Division.

"Sematech has involved most if not all of the companies that have a stake," Kalk said, including the maskmakers. Although he vows that Toppan Photomasks will be there if EUV succeeds, there is still much to consider before the company decides how much it can afford to chip in to the effort.

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