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Scientists Develop Novel 14-nm Scallop-Shaped FinFETs on Bulk-Si Substrate
Author: Dept.10 MA Xiaolong;Translate by Dan
Update time: 2015-07-09
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To overcome serious scaling issues, multi-gate fin fieldeffect transistors (FinFETs) with 3D fin-shaped channels have been extensively explored for many years as a new device platform and have been recently introduced into mass production with cutting-edge process technologies. Excellent short-channel-effect (SCE) immunity is achieved for FinFETs owing to the strong gate control of the double gates in the fully depleted fin channels. In addition, the fabrication technology of FinFETs is a quasiplanar process and more compatible with the conventional planar process than previous vertical double-gate devices.   

Recently, scientists from Integrated Circuit Advanced Process Center of the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS) developed novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) technology. S-FinFETs are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins.  

By using this technology, scientists fabricated p-type S-FinFETs with 14-nm physical gate length and 75 mV/dec SS, 62 mV/V DIBL, which are much better than those of normal FinFETs with a similar process. The test results indicate that the S-FinFET demonstrates an obvious scaling advantage over the normal FinFET for sub-10-nm node CMOS process applications. By slightly modifying the fin etching process of the normal FinFET process, the new devices have achieved excellent DIBL and SS as LG scaled down below 20 nm. The variability has no obvious degradation. The research results, published in the Nanoscale Research Letter, were highly recommended by reviewers, saying "it is likely to be one of the important technologies for the next generation of FinFET technology". 


Figure 1:Schematic Illustrations of S-FinFET Design and Channel Control Capability  

a- Design Diagrams of Device Structure and Process Integration Flow for S-FinFETs  

b- Channel Cross-Sectional Views and TCAD Simulated Channel Leakage Density Mapping Images for Nanowire FET, Normal FinFET,and S-FinFET 

This work was supported by “16/14nm Basic Technology Research” of national 02 IC projects in China (No. 2013ZX02303). The study has been published in Nanoscale Research Letters.XU W, YIN H, MA X, et al. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate [J]. Nanoscale Research Letters, 2015, 10(1): 249. 


Researcher ZHAO Chao

E-mail: zhaochao@ime.ac.cn

Website of Dept.http://english.ime.cas.cn/Research/ResearchDivisions/LAB10/ 

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