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Dr. Zhigang Ji Visited IMECAS
Author: Microelectronics Key Lab ZHANG Kangwei
Update time: 2016-09-12
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On September 7 2016, Dr. Zhigang Ji from Liverpool John Moores University visited the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS). He delivered a lecture entitled “Advanced CMOS device characterization and modelling for reliability-aware device/circuit co-design” in IMECAS hosted by associate Prof. Jinshun Bi. More than 40 local professionals and graduate students attended the meeting.   

As semiconductor manufacturing migrates to advanced technology nodes, circuit reliability can no longer be overlooked during the early stage, but dynamically dependent on circuit operations during the course of its operation. Increasing severity of reliability challenges and higher error rates in the circuit and system boosts the request of design for manufacturability, aiming to optimize the design in terms of performance, reliability, power consumption and cost. The heart of this mission lies in reliability aspect for CMOS devices and their interaction with the circuits, however, conventional models and characterization techniques are known to be no longer adequate. In this talk, Dr. Zhigang Ji discussed their Defect-centric As-Grown-Generation (A-G) framework and its integration with commercial circuit simulator. The framework had been experimentally proven to be an accurate and general model for sub-22nm technology. Dr. Zhigang Ji also shared the experience how this framework had boosted the recent improvement of IMEC’s advanced Ge/III-V device technology development. The new points of his research on reliability made a big splash and reached an academic discussion.  

After the lecture, a symposium was held with the participating researchers from the IMECAS, both sides introduced their recent works and had a heated discussion.   


Prof. Ji was giving a talk.  


Dr.Zhigang Ji is currently a Senior Lecturer at Liverpool John Moores University (LJMU). He received ME from Peking University in 2006 and PhD from Liverpool John Moores University (LJMU) in 2010, both majored in Microelectronics. His recent research focuses on the degradation phenomena and reliability modelling for advanced logic and memory devices with advanced materials and structures as well as the interaction within circuit and system. He has co-authored more than 60journal and conference papers including 11presented in IEDM and VLSI. Several of his research outputs have been adopted by the industry including one characterization technique integrated into Keithley Instruments product. He is serving at various functions for the journals and conferences from various academic publishing groups including IEEE, IET, and Nature. He is distinguished IMEC academy lecturer since 2015 and is currently an executive member of Gyancity Research Lab Private Limited responsible for coordinating research and development activities in the field of engineering and technology in Europe and Asia.  

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