October 13, 2016, EDA center of Chinese Academy of Sciences and Synopsys (EDACAS) jointly organized a TCAD technology seminar in IMECAS. It is mainly about simulation strategies for advanced semiconductor technologies. Participants included the relevant technology and marketing personnel from Synopsys, more than 40 academics researchers and technology development professionals from IMECAS, Tsinghua University and other units. 

The Seminar comprised of two parts. In the first part, the speaker Ric Borges Sr. gave a report named Product Marketing Manager from Synopsys, which highlighted the market trends of the semiconductor industry and its impact on the development of TCAD tools. He mentioned that there is great need for designers to have more choices among architecture, processes and materials while working at < 13nm (logic) and < 1nm (memory). There is also continuous need of scaling as well as the necessary for new architectures. The speaker highlighted that the Synopsys launched pre-wafer simulation solution to reduce the semiconductor process development time, and make it possible to shift left the research phase to start pathfinding and selection at very earlier stage of development. Synopsys initial phase path finding DTCO supports material modeling and quantum transport modeling. In the next section, speaker highlighted the Synopsys TCAD framework for delivering the accuracy (Centurus, Process Explorer), methodology calibration (Robust Mesh, Fast Track 3D Mode) and runtime performance (Parallel Computing scaling) in brief detail. At the End, the speaker highlighted the use of Synopsys TCAD tools for the development of power and memory devices and discussed image sensors in detail. 

The second phase of the seminar was entitled as Advanced Logic Development, starting with the development challenges in the advances logic, especially under the trends of increasing complexity. Advanced FinFETs and Nanowires also drives the new challenges. The discussion further extended to the material modeling for TCAD followed by the advance transport in post-FinFET-structures. The speaker also highlighted the MOL and BEOL capacitance and resistance modeling. In the end of the second half of the seminar, the speaker highlighted the process explorer application in the devices architecture exploration and integration. 

In the end, three lucky draw prizes have been drawn among the participants of the seminar.