On September 8 2016, Prof. Steve S. Chung from National Chiao Tung University visited the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS). He delivered a lecture entitled “A New Architecture of Single-transistor NVM Feasible for Embedded Applications” in IMECAS hosted by Prof. Shibing Long. More than 40 local professionals and graduate students attended the meeting.
In the research of the replacement for Floating gate and SONOS, RRAM seems to be a potential candidate because of simple implementation and the easy integration with the VLSI process. However, the time-to-market for RRAM seems to be slowed down as a result of sneak path, forming current, and uniformity issues, especially at the circuit level. In this talk, Prof. Steve S. Chung proposed a one transistor resistance-gate nonvolatile memory (NVM) which comprised a simple MIM structure on top of the transistor gate while readout was taken from the transistor Vth or Id, similar to that of flash memory. A bilayer MIM was preferable for quality performance. Results demonstrated that this memory exhibits large window, excellent endurance, retention, and can solve the sneak path and forming issues in conventional crossbar RRAM. The architecture of this NVM cell was superior to the 1st generation floating-gate and the 2nd generation SONOS NVMs, and was fully compatible with the logic CMOS technology and well-suited for both NOR and NAND memories, especially for future embedded applications. The new points of his research on RRAM and NVM made a big splash and reached an academic discussion.
After the lecture, a symposium was held with the participating researchers from the IMECAS, both sides introduced their recent works and had a heated discussion.
Prof. Chung was giving a talk.
Biography
Currently, STEVE S. CHUNG is NCTU and UMC Chair Professor at the National Chiao Tung University (NCTU). After joining NCTU in 1987, he has been the first Department Head of EECS Honors Program (2004-2005), Dean of International Affairs Office and Executive Director of school level research center, (2007-2008). He was a Research Visiting Scholar with Stanford University in 2001, visiting professor to University of California-Merced in 2009-2010, and taught graduate courses at Stanford and UC-Merced in the Fall of 2009. He was also an honorary professor of the Institute of Microelectronics, CAS. He has been the consultant to the two world largest IC foundries, TSMC and UMC. His recent current research areas include- nanoscale CMOS devices and technology; low voltage/power design Tunneling FET, nonvolatile memory technology and reliability; and reliability physics/interface characterization. By the end of 2015, he has than 26 times oral presentations in the IEEE flagship conferences, IEDM and VLSI. In particular, he was the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995.
He is an IEEE Fellow, the current IEEE EDS BoG(Board of Governor) member, IEEE Distinguished Lecturer, EDS Taipei chapter chair, Editor of J-EDS, and with past involvement as EDS AdCom member (2004-2009), EDS Regions/Chapters Vice-Chair and chair, and Editor of EDL(2002-2008). He has served on various important conference committees, e.g., VLSI Technology, IEDM, IRPS, IPFA, ICMTS, SNW, VLSI-TSA, SSDM etc. He was awarded 3 times outstanding Research Award, distinguished PI, and distinguished NSC Research Fellow, from the National Science Council; Distinguished EE Professor and Engineering Professor of the Engineering Societies in Taiwan. He received 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.
