Name:LI Jia
Gender:Female
Title:Associate Professor
Nationality:P.R.China
Education:PhD
E-Mail:lijia@ime.ac.cn
Address:3 Beitucheng West Road, Chaoyang District, Beijing, PR China
Postcode:100029
Tel:+86-10-82995779 

 
Education Background:
2004.09-2009.06, Institute of Computing Technology, Chinese Academy of Sciences, PhD degree
2000.09-2004.06, University of Science and Technology Beijing, Bachelor’s degree
Professional Experience:
2009.07-2011.06, Tsinghua University, Assistant Professor
2011.06 till now, Institute of Microelectronics, Chinese Academy of Sciences, Associate Professor

 
Research Interests:
Testing, Design-for-Testability (DfT) and Power-Aware Design of Very Large Scale Integrated (VLSI) Circuits and Micro-Electromechanical Systems

Publications:
Books:
[1] 《Test Optimization of Digital Integrated Circuits》，Beijing：Science Press，June 2010，ISBN：978-7-03-027894-4
Journal papers:
[1] Jia Li, Qiang Xu, Yu Hu, and Xiaowei Li，“X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing, ” IEEE Transactions on Very Large Scale Integration Systems, 18(7), pp. 1081-1092, 2010.
[2] Jia Li, Yu Hu, Xiaowei Li, “Scan Chain Design for Shift Power Reduction in Scan-based Testing”, Science China F: Information Sciences, 54(4), April 2011, pp.767-777.
[3] Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li and Qiang Xu, “Capture-power-aware test data compression using selective encoding”, Integration: The VLSI Journal, 44(3), June 2011, pp. 205-216.
[4] Jia Li, Yu Hu, Xiaowei Li, Wei Wang. SCANGIN：An Approach for Reducing Dynamic Power in Scan-based Testing，《Journal of Computer-Aided-Design and Computer Graphics》，Vol.18，No.9，pages 1391-1396，2006.
[5] Jia Li, Yongjun Xu, Xiaowei Li, Xinping Wang. Power Analyzing Method in Computer Architecture-level，《Journal of System Simulation》，Vol.16，No.12，pages 2821-2824，2004。
International Conference papers:
[1] Jia Li, Qiang Xu and Dong Xiang, “Compression-Aware Capture Power Reduction for At-Speed Testing”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2011, pp. 806-811.
[2] Jia Li, Yu Huang and Dong Xiang, “Prediction of Compression Bound and Optimization of Compression Architecture for Linear Decompression-based Schemes”, IEEE VLSI Test Symposium (VTS), Dana Point, USA, 2011, pp. 297-302.
[3] Jia Li and Dong Xiang, “DfT Optimization for Pre-Bond Testing of 3D-SICs containing TSVs”, Proc. International Conference on Computer Design (ICCD), Amsterdam, Netherlands, paper 33, 2010.
[4] Jia Li, Xiao Liu, Yubin Chen, Yu Hu, Xiaowei Li, and Qiang Xu. “On Capture Power-Aware Test Data Compression for Scan-Based Testing”, Proc. International Conference of Computer-Aided Design (ICCAD), San Jose, USA, pages 67-72, 2008.
[5] Jia Li, Qiang Xu, Yu Hu and Xiaowei Li. “iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing”, Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Munich, Germany, pages 1184-1189, 2008.
[6] Jia Li, Qiang Xu, Yu Hu and Xiaowei Li. “On Reducing Both Shift and Capture Power for Scan-Based Testing”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, pages 653-658, 2008.
[7] Jia LI, Yu HU, and Xiaowei LI. “A Scan Chain Adjustment Technology for Test Power Reduction”, Proc. IEEE 15th Asian Test Symposium (ATS), Fukuoka, Japan, pages11-16, 2006.
[8] Jia LI, Qiang XU, Yu HU, and Xiaowei LI. “On Improving Channel Utilization in Testing NoC-Based Systems”, Dig. of 12th IEEE European Test Symposium (ETS), Freiburg, Germany, 2007.
[9] Jia LI, Qiang Xu, Yu Hu and Xiaowei Li. “Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction”, Proc. IEEE International Symposium on Electronic Design, Test & Applications (DELTA), Hong Kong SAR, pages 26-31, 2008.
[10] Jia LI, Yu HU, and Xiaowei LI. “Test Cost Efficiency Exploration for CMT Processors”, Proc. IEEE TENCON, Taipei, 2007.
[11] Jia LI, Yu HU, Xiaowei LI. “Impact-Factor-Guided X-Filling for Peak Power Reduction during Test”, Proc. IEEE TENCON, Taipei, 2007.

Patents Application:
(1) A Test Wrapper Circuit and Its Design Method. Patent authorization number：ZL200610090243.4
(2) A Test Access Circuit for Core Multiprocessor (CMP) and Its Design-for-Testability Method. Patent authorization number：ZL200710304267.X

Projects and Subjects Participated:
1. As Project Leader:
1) 2009.12，Open Project from Key Laboratory of Computer System Architecture of Chinese Academy of Sciences: Co-optimization of Test Power and Test Compression for Digital Integrated Circuits. (ICT-ARCH200902)：2010.01 - 2011.12；
2) 2010.06，China Postdoctoral Science Foundation funded project: Research on Analyzing Method for Co-optimization of Test Data Volume and Test Power（20100470014）: 2009.07-2011.06；
3) 2010.07，National Nature Science Foundation of China (NSFC) project: Research on Co-optimization of Test Compression and Test Power based-on Analysis of Test Patterns（61006017）: 2011.01-2013.12。
2. As Main Member:
1) National Nature Science Foundation of China (NSFC) projects（90207002, 60633060, 60606008, 60803031, 60910003）
2) National 863 Plan projects（2007AA01Z107, 2007AA01Z113, 2009AA01Z129）
3) National 973 Plan projects（2005CB321604, 2005CB321605）