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HAN Zhengsheng
Update time: 2009-10-12
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NAME: HAN Zhengsheng (Ph.D. Director)
Title: Professor
Email: zshan@ime.ac.cn
Microelectronics and Solid state Electronics
Undergraduate: Xi’an Jiaotong University
Degree: Master Degree
Major: Semiconductors and Devices
Studying abroad: Visitor scholarship in Hong Kong University of Science& Technology
Apr. 1997—present: Institute of Microelectronics CAS ( the old name: Microelectronics R&D Center CAS). Research on IC technology and IC design. Management of post graduates and administration of department.
The former position: Senior engineer, in charge of photolithograph process, vice director of department and principal of testing process concurrently, principal of product branch in Si engineering center, and principal of projects.
Now director of Si devices & integrated technology department, the member of the party committee of institute, the member of the institute committee of employee representatives, the member of institute academic committee, the member of institute degree committee.
Research fellow, Professor of graduate school CAS, Ph.D. director, the gainer of the national special subsidy.
Apr. 1994—Mar 1997: institute of precision microelectronics, Beijing, research on design of IC, in charge of technology.
Sept. 1993—Mar. 1994: Beijing Yingfa scientific and technological company. Research on design of IC, vice manager of IC branch.
Jun. 1988—Aug. 1993: Beijing Yandong microelectronics united company. Research on technology of IC, in charge of novel product development and product line, engineer, director of workshop, chief engineer.
Jul. 1983—Aug. 1985: factory 878, ministry of electronic industry, research on technology of IC, in charge of diffusion process.
(1)《semiconductor manufacturing technology》,publishing house of electronics industry, Jan. 2004 (version)
(2)《SOI CMOS technology and its application》,chapter 6, publishing company of science.
(3)《materials engineering dictionary of china》,Vol.11, chapter 3, section 3. publishing company of chemistry industry.
(4)“High performance 27 nm gate length CMOS device with EOT 1.4 nm gate oxynitride and strained technology” 7th International Conference on Solid-State and Integrated Circuits Technology Proceeding, Beijing ,China, Oct. 18-21,2004,Vol.1, Oct. 2004, P.47-53.
(5)“SOI Active and Passive Integrated Devices for RFIC Applications” 7th International Conference on Solid-State and Integrated Circuits Technology Proceeding, Beijing ,China, Oct. 18-21,2004,Vol.1, Oct. 2004,P.186-189
(6)Electrical characteristics of the rf-excited oxygen plasma-cathodization-grown SiO2/Si interface Applied PhysicsA 1996,62,391-395
(7)The Investigation of Key Technologies for Sub-0.1um CMOS Decice Fabrication IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.48,NO.7,p1412-1420
(8)Characterization of 1.9-amd 1.4-nm Ultrathin Gate Oxynitride by Oxidation of Nitrogen-implanted Silicon Substrate IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.51,NO.1,JANUARY 2004,p113-120
(9)SOI Technology for Radio-Frequency Integrated-Circuit Applications IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.53,NO.6,JUNE 2006,p1310-1316
(10)High performance 36nm gate length CMOS device and key technology International Conference on Materials for Advanced Technologies(ICMAT),2003,Invited paper
(11)High-Voltage CMOS process for Field Emission Display Drivers Technical Digest of the 18th International Vacuum Nanoelectronics Conference(IVNC 2005),Oxfoed,UK,p344-345
(12) An Asymmetrical Source/Drain Junction Structure for SOI RFIC: Immune to Floating Body Effects IWJT-2004, shanghai, 2004.p.273-276
(13)Model Parameters Extraction of SOI MOSFETs IWJT-2006, shanghai, 2006.p.240-243
(14)20nm polysilicon gate patterning and application in 36nm complementary metal-oxide-semiconductor devices. J.Vac. Sci.Technol.B 21(6),Nov/DEC 2003,p2352-2359
(15)Fabrication of submicron trackwidth thin-film head and its inductance-saturation characteristics. Journal of Magnetism and Magnetic Materials 279(2005)59-63
(16)An analytical model of partially depleted SOI MOSFET based on BSIM3V3. Journal of Functional Materials and devices,2006,Vol.12.No.1:p.67-70
(17) PDSOI NMOSFETs with H shape gate. Journal of Functional materials and devices, 2005, Vol.11, NO.1, p71-74.
(18) Study on SOI RF devices and its integration technology, Journal of Functional materials and devices, Jun. 2005, Vol.11, NO.2, p177-182.
(19)Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs Chinese Journal of Semicongductors,2005, Vol.26, No.2, p.234-237
(20)Off-State Breakdown Characteristics of Body-Tied Partial-Depleted SOI nMOS Devices Chinese Journal of Semicongductors,2005,Vol.26,No.4:p.656-661
(21)A Novel Local-Dielectric-Thickening Technique for Performance Improvements of Spiral Inductors on Si Substrates. Chinese Journal of Semicongductors,2005,Vol.26,No.5:p.857-861
(22)Design and Fabrication of a High-Voltage nMOS Device. Chinese Journal of Semiconductors, 2005,Vol.26,No.8:p.1489-1494
(23)The analytic threshold-voltage model for fully depleted SOI MOSFETs. Chinese Journal of Semicongductors,2005,Vol.26,No.12:p.2303-2308
(24)SOI MOSFET Model Parameter Extraction via a Compound Genetic Algorithm. Chinese Journal of Semiconductors,2006,Vol.27,No.5:p.796-803
(25)CMOS/SOI 64Kb SRAM, Journal of Semiconductors, 2001 Vol.22 NO.1, p47-51.
(26) Simulation of A Novel Schottky Body-Contacted Structure Suppressing Floating Body Effect in Partially-depleted SOI nMOSFETs. Journal of Semiconductors, 2002, Vol.23, NO.10, p1019-1023.
(27)Floating Body Effect in Partially Depleted SOI NMOSFET with Asymmetric Structure and Ge-Implantation Journal of Semiconductors, 2002, Vol.23, NO.11, p1154-p1157
(28)Breakdown Characteristics of N_2O-Annealed H_2-O_2 Grown Thin Gate Oxide.  Journal of Semiconductors, 2002, Vol.23, No.11, P1207-1210.
(29)Design and Simulation of High-Voltage CMOS Devices Compatible with Standard CMOS Technologies. Journal of Semiconductors, 2003, Vol.24, No.7, P758-762.
(30)Dependence of Hole Mobility in PDSOI PMOSFET on Isolation Process. Journal of Semiconductors, 2004, Vol.25, No.10, P1345-1348.
(31)Fabrication of Thin Gate Oxide High-Voltage CMOS. Journal of Semiconductors, 2004, Vol.25, No.5, P568-571.
(32)Radiation of SOI MOSFET with Shallow Source. Journal of Semiconductors, 2004, Vol.25, No.6, P.735-739.
(33)Model Parameters Extraction of a BSIM SOI Model Based on the Genetic Algorithm. Journal of Semiconductors, 2005, Vol.26, No.8, P1676-1680.
(34)A Radiation Hardened SOI Inverter. Journal of Semiconductors, 2005, Vol.26, No.9, P1829-1832.
(35)The Research of Fully-Depleted Thin-Film SOI CMOS Devices and Circuits with N + Poly Gate. Chinese Journal of Electron Devices,Vol.27,No.1,2004:p.69-71
(36)Study of the Parasitic Bipolar Transistor in PD SOI NMOSFETs. Chinese Journal of Electron Devices,Vol.27,No.4,2004:p.575-577
(37)Total Dose Radiation Hard NMOSFETs. Chinese Journal of Electron Devices,Vol.27,No.4,2004:p.578-580
(38)Overview of SOI DTMOS (Dynamic-Threshold MOSFET). Chinese Journal of Electron Devices,Vol.28,No.3,2005:p.
(39)Novel BTS Structure Technology for Partially Depleted SOI MOSFET. Chinese Journal of Electron Devices,Vol.28,No.4,2005:p.730-732
(40)The Influence of Body Resistance on the Speed Characteristic of BC(body contact) Digital D Flop-Flop Circuit on SOI. Chinese Journal of Electron Devices,Vol.28,No.4,2005:p.778-781
(41)Impact of Dielectric Layer Deposited by PECVD on Performance of MOSFET. Chinese Journal of Electron Devices,Vol.29,No.1,2006:p.1-4
(42)Thin Film Thickness Effect on 0.1μm Dimension SOI Groove Gate Device Characteristics. Microelectronics & Computer,Vol.23,No.5,2006:p.28-30
(43)Study of Dual Gate Oxide Technology in CMOS Process. Microelectronics & Computer,Vol.22,No.11,2005:p.5-6
(44)Performance Degradation of NMOS Device in Oxide Plasma Ambience. Microelectronics & Computer,Vol.22,No.8,2005:p.3-6
(45)MOSFET Models and Parameter Extraction. Microelectronic technology, Aug. 2003, Vol.31, No.4, P23-28.
(46)A Novel Structure of SOI RF IC and Its Process Technology. Microelectronics, 2004, Vol.34, No.5, P569-571。
(47)Electrostatic Discharge Experiment for CMOS/SOI 64-kB SRAM`s. Microelectronics, 2004, Vol.34, No.6, P636-639。
(48)High-Voltage CMOS Devices for FED and PDP Driver IC. Chinese Journal of Luminescence, 2005, Vol.26, No.5, P678-683.
(50)Investigation of key Technologies for 100V HVCMOS Process. Chinese Journal of Semiconductors,2006,Vol.27,No.11:p.1900-1905
(51)Investigation on Interface Planarization of Driver IC for Storage Cells of MRAM. Journal of Semiconductors, 2006, Vol.27, No.12, P358-360.
(52)Study of Improved Performance of SOI Devices and Circuits. Journal of Semiconductors, 2006, Vol.27, No.12, P322-327.
(53)High Performance Gate Length 22nm CMOS Device with Strained Channel and EOT 1.2nm. Journal of Semiconductors, 2006, Vol.27, No.12, P283-290.
(54)fabrication of 100V high voltage PMOS devices. Journal of semiconductor, 2006 Vol. NO.12, P358-360.
(55)A High Performance 0.18μm RF nMOSFET with 53GHz Cutoff Frequency. Chinese Journal of Semiconductors,2006,Vol.27,No.8: p.1343-1346
(56)SOI Technology for Radio-Frequency Integrated-Circuit Applications. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.53, NO.6. JUNE 2006 p.1310-1316
(57)Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.54, NO.6. JUNE 2007 p.1394-1401
(58)Total Dose Radiation Hardened PDSOI CMOS 64k SRAMs. Chinese Journal of Semiconductors, 2007,Vol.28,No.8: p.1184-1186
Jan. 1997-Dec.1999 national important program to tackle key scientific and technological problems:“study on submicron CMOS/SIMOX devices and circuits”, (sort order: 2)checked and accepted,
1997-2000 national important program to tackle key scientific and technological problems: “study on key technology of 0.35µm IC”, (sort order: 13) checked and accepted.
1997-2000 national important program to tackle key scientific and technological problems: “study on structure and performance of 0.1µm CMOS devices”, (sort order: 18), checked and accepted.
1997-2000 national important program to tackle key scientific and technological problems: “study on technology of electronic beam exposure”, (sort order: 5), checked and accepted.
1997-1999, organized and took part in the project about the match of E-BEAM and STEPER lithography, choice of E-BEAM photoresist and testing of SAL601. This is the key part of the above-mentioned 3 projects.
1999-2000 one of principal of information innovation of CAS. Checked and accepted.
Apr.2001-Dec.2002, principal of scientific and technological project of Beijing government: “study on technology test line of ultra-large scale IC”, checked and accepted. So far, it has been totally increasing income over 3,000,000¥.
Currently taking part in national important basic research, “973” program “basic research of key technology and fabrication of 20-50nm devices”, in charge of layout. “973”program: “basic research of novel field emission flat panel display and microdisplay, number: 2003CB314705, study on driver circuits of field emission and microdisplay and its integrated technology”.
Chinese patent: ZL02147232.7 “fabrication method of a kind of oxynitride film”,authorized, sort order: 4.
Chinese patent: 200410035088.7, “A novel self-aligning technology to be used to RF transverse diffusion FET”, accepted, sort order: 5.
Chinese patent: 2004 10045979.0 “integrated structure and fabrication method of insulated si for IC”, accepted, sort order: 5
In 2004, Scientific and technological first-class prize of Beijing government because of “study on high performance CMOS devices with a gate 27nm long and its key technology, as main research fellow, sort order: 3.
In 2002, Scientific and technological second-class prize of Beijing government because of “study on key technology of 0.18/01µm CMOS IC”, as main research fellow, sort order: 7.
In 2003, excellent paper prize by electronic academic committee seminar of china because of “CMOS/SOI 4Kb SRAM”, main research fellow, sort order: 3.
Assessing expert of programs of national natural science foundation of china.
Referees of “Journal of semiconductor”, “Journal of computer science and technology”, “Xi’an JiaoTong university”, “Journal of scientific technological university of china”, “Journal of ZeJiang university”. Member of the 14th national semiconductor IC academic committee and Si materials annual academic committee.
Member of organization committee of Agilent cup on Match of semiconductor manufacturing technology.
Program committee member of 2006 international junction seminar(International workshop on Junction technology, IWJT).
Member of the 4th electrical power and electronic academic council of Beijing.

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