Address 3 Beitucheng West Road, Chaoyang District, Beijing, PR China
09/2004 – 03/2007 Master of Engineering in Physical Electronics, Institute of Optoelectronic Science and Engineering, Huazhong University of Science and Technology.
09/1999 – 07/2003 Bachelor of Engineering in Communication Engineering, Department of Electronic and Information Engineering, Huazhong University of Science and Technology.
08/2008 - Present Team Leader
Dept.of Electronics System Technology, Institute of Microelectronics of Chinese Academy of
03/2007 - 07/2008 Team Leader
Laboratory for Photonics Integrated Technologies, Shenzhen Institute of Advanced Integration
Technology, Chinese Academy of Sciences/The Chinese University of Hong Kong, Shenzhen
System-in-Package (SiP) / Multi-Chip Module (MCM) design.
High-speed hardware design.
《Cadence SiP Design: Allegro SiP / APD Design Guide》