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Name:ZHU Huilong
Gender:Male
Title:Chief Scientist of IC Advanced Process R&D Center, the Institute of Microelectronics of Chinese Academy of Sciences
Education:Ph.D
E-Mail:zhuhuilong@ime.ac.cn
Address:3 Beitucheng West Road, Chaoyang District, Beijing, PR China
Postcode:100029
Tel:+86-10-82995769
Education Background:
Dr. Zhu obtained his B.S. in 1982 in physics at University of Science and Technology of China (USTC) and his Ph.D in 1988 in physics at the Beijing Normal University, Beijing, China.
Professional Experience:
Dr. Zhu worked at Argonne National Laboratory in 1990-1992 (Visiting Scholar), University of Illinois at Urbana-Champaign in 1992-1996 (Visiting Assistant Professor), Digital Equipment Corporation in 1996-1998 (Principal Engineer), Intel in 1998-2000 (Senior Engineer), and IBM in 2000-2009 (Advisory Engineer). He was an IBM Corporate Leading Inventor and an IBM Master Inventor. He is co-inventor of Dual Stress Liner Technique and Stress Proximate Technique, which have been widely used to enhance CMOS performance. He is also co-inventor to use recessing gate to enhance stress in the channel of a strained MOSFET, which is applied, as a key technology, to high-k metal gate CMOS products.
Dr. Zhu obtained more than190 issued US patents and published over 50 technical papers.
Research Interests:
Nano MOSFET and Advanced CMOS Technology.
Publications:
Selected publications:
1) H. Zhu et al, “Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner,” VLSI 2007, pp180-181
2) H. Zhu et al, “On the Control of Short Channel Effect for MOSFETs with Reverse Halo Implantation,” IEEE Electron Device Lett., vol. 28, no. 2, pp168-170, 2007。
3） H. Zhu, “Modeling of Impurity Diffusion with Vacancy-Mechanism in Diamond Lattice and Si1-xGex,” Electrochemical Society Proceedings Volume 2004-07, pp. 923-934
4) H. Zhu and R. S. Averback, "Sintering Processes of Two Nanoparticles: A Study by Molecular-Dynamics Simulations," Phil. Mag. Lett. 73, no.1, (1996): 27-33.
5) H. Zhu et al, “Molecular-Dynamics Simulations of a 10-keV Cascade in Beta-NiAl,” Philosophical Magazine A71 735-758, 1995
Honour:
IBM Corporate Leading Inventor;
IBM Master Inventor.
Patents Application:
Selected Patents:
1) H. Zhu et al, “Structure and method to enhance stress in a channel of CMOS devices using a thin gate,” US Patent application number: US20060160317A1
2) H. Zhu et al, “Structure and method for manufacturing planar SOI substrate with multiple orientations,”US7094634.
3) H.S. Yang and H. Zhu, “Method and apparatus for increase strained effect in a transistor channel,” US7118999 and US7462915
4) K. Lee and H. Zhu, “Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom,” US7163867
5) B. Doris et al, “Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers,” US8008724B2
Projects and Subjects Participated:
Chief Scientist of Exploratory Research and Platform for Advanced CMOS Technology (2009-2012). This work is funded by "National S&T Major Project 02"
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