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Update time: 2009-10-10
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NAME: CHEN Lan       

Degree: Ph.D

Address: No.3 Bei tucheng west road, chaoyang district Beijing

Zip: 100029

Tel: (08610)13911508171 


E-mail: chenlan@ime.ac.cn

Professor, Computer Science and Microelectronics Director of the 7th Research Lab of Institute of Microelectronics

1997-2001, got Ph.D degree at the Institute of Computing Technology, Chinese Academy of Sciences. 

Major: High Performance Computer Architecture

Thesis: Application wave pipelining technologies in deep submicron SOC system design.

1988-1991, got master degree at the Institute of Microelectronics, Xian, Shaanxi province

Major: Computer Architecture and VLSI design

Thesis: A cell-based gate array basewafer generator

1984-1988, got Bachelor degree in Department of Computer Science and Technology, Sichuan University, Chengdu, Sichuan.

Design for Manufacture for nanometer ICs. 

SoC/IP design methodologies, low power design technologies,

NVM driver circuits IP,

Wireless wide band media IC physical realization design methodologies,

Wireless sensor network base band chip design,

Very high speed interface IO circuits for high performance computing system.

Oct 2006-now   EDA Center of CAS, Institute of Microelectronic, Chinese Academy of Sciences 

Job Title: Director of Electronic common technologies department, of IME

Deputy Director of EDA Center of CAS Professor  

Aug 2003-Oct 2006 Company: Institute of Computing Technologies Suzhou Branch, Chinese Academy of Sciences (Suzhou CAS IC Design Center)

Job Title: Vice President

In charge of building Suzhou CAS Center’s technology development direction, technology developing and marketing team and systems for project management.

Company: Institute of Computing Technology, Chinese Academy of Sciences 

1996-Oct 2006

Job Title: Professor and Supervisor for postgraduate students

The research area is very high performance digital system design technology, VDSM design method and EDA technology and SoC design methodology.   
) Achievement in marketing strategiesIn merely one year, built Suzhou IC design center’s business mode, built VPN to service IC design house by network and signed 1million RMB contract in less than 6months.After discovering that the design houses in Suzhou area were short of IC design engineers, I built the customizing IC engineer training business mode and earned 50KRMB in two months.) Achievement as a manager 

1991-1996   Company: Microelectronics Center, Aerospace Industry Ministry.

Job Title: IC Design Engineer and project manager

As a supervisor, project manager and key member, I take part in many important research projects, which are supported by national fund. 

2007- up “Wireless Sensor Network chip sets design ”, supported by National Science and technologies 863 project

2006-up “IP common technologies design”, supported by CAS fund

2006-up “DFM technologies”, supported by IME

June 2005-up to now, Project manager of the “IC design methodologies platform building”, supported by Jiangsu Science and Technology Department, which is still developing.

Jan.2005-up to now, Project manager of the important IC foundational construction project, “Jiangsu IC test service center”, which is supported by Jiangsu Science and Technology Department. This project is still progressing .

2003-2005, Project manager of the project “Application wave pipelining technologies in deep submicron SOC system design”; this is supported by the National Natural Science Foundation of China and is still ongoing.

2003-2004, Project manager of the project “Kernel technologies research for high performance CPU design”. As a principal, I was in charge of the affiliate project, “Research of key technology and practical scheme of high performance common CPU and the design strategies”, which was supported by the National 863 high technologies project. The research result has been used in Godson2 developing and reached the design target.

2001-2003, Key member of the important innovative project “high performance general purpose CPU developing and industrialization” of CAS and key member of the important project of National 863 high technologies project “High performance generic CPU (godson) development”. I was responsible for IC physical design team’s construct, physical design strategies, and IC design methodologies research.

Contributions: Built the Godson1 CPU’s physical design strategies, including the design methodologies, manufacturing process, packaging and testing. In the mean time to find the pattern who will cooperate my effort, the Godson is the first project in mainland to get the TSMC 0.18CMOS deep submicron silicon processing support. Right now, the Godson group has already built up long term, cooperative relationships with these partners. I’ve suggested the “high performance ASIC” design strategies for CPU development, a technology roadmap which the Godson2 and Godson3 will use. With the strategies I have pointed out, the Godson2 has reached its design target.

2002-2003, Project manager of “SoC’s architecture research” supported by ICT’s Youth fund; this project has been completed.

2001-2002, Project manager of “Very deep submicron IC design methodologies research”, which was supported by ICT’s Youth fund.

1998-2001, Key member of “Application wave pipelining technologies in ASIC design” supported by National Natural Science Foundation of China. Responsible for the project research strategies and main research work.

1996-1998, Key research member of “kernel research problems in high performance computing technologies” supported by the National Pandeng project. Responsible for very high speed digital circuit design methodologies research.

1992-1995, Project manager of “ASIC CAD system development and CAT technologies application research” supported by the National Defense Ministry’s the eighth five project fund. Responsible for the sub-project “HCMOS laser ray gate array basewafer’s research”.

1994-1995, Key member of “parallel computing technology and parallel algorithms research” supported by NFSC.

1991-1993, Key member sent to abroad to get three months long IC design technologies training in Switzerland .


1. As a founder of the Suzhou CAS IC design center and the IC design platform in Institute of Computing Technology, CAS, I have built up a technology and marketing team with 100 people in less than two years; we have already received financial support for our research project from local government.

2. Served as a key member of the consultant group which constructed the EDA center of CAS. Contributions: For the three centers, I’ve made the EDA design platform strategies, decided the center’s future development area; I have also decided the center’s business mode et al.

3. As the vice president of the Suzhou IC design center, I was responsible for hiring technology engineers, building the technology teams and building the internal management strategies. As of now, the work has already been finished.

4. As a project manager, I have led a 5 person team to complete the northbridge chips physical design and passed after a single attempt.

5. I have led a 15 person team as a project manager to complete two types of millions gates scale digital IC product physical design passed on the very first attempt.

6. Serving as a team manager, I finished the Godson1 backend physical design.

7. As a project manager and key engineer, I completed the Gate array basewafer design and tape out.

8. As an engineer, I have finished several ASIC designs for aerospace application.

IEEE CS member. 

Professor of the nanometer IC design research center of the CAS(Chinese Academy of Sciences) EDA center.

Consultant member of the CAS EDA center.

Program committee member of the conference of Chinese computer technology, 2005.

Program committee member of the International conference of High Performance Computing Asia, 2005.

1995, Awarded the Science and Technology improvement prize of Aerospace Industry Ministry. 

2003, Awarded the Outstanding Science and Technology Achievement of the Chinese Academic of Sciences


1. “A non-complementary CMOS circuit architecture used for wave pipelined circuit delay balance”. Patent No. ZL01135045.8

2. “A kind of low cost grid array package technology”, accepted No. 200710122481.3

Design for Manufacture for nanometer ICs. SoC/IP design methodologies, low power design technologies, NVM driver circuits IP, wireless wide band media IC physical realization design methodologies, wireless sensor network base band chip design, very high speed interface IO circuits for high performance computing system. 

High performance CPU physical design Technology. High speed digital circuit design and EDA technology. Deep submicron VLSI design technology. VCSEL spectra-electricity transform circuit design technology.

[1] Chenlan、Shen xubang, “Creating arithmetic based on half-custom piece of cell building tree”. Microelectronics and computer, Apri, 1998. 

[2] Chenlan、Zhimin Tang,“Transporting Design Data on Netlist Level: A Practical Application Example”,in Proceedings of the Third International Conference on ASIC, 318-321, August 1998.

[3] Chenlan、Zhimin Tang,“A Semi-custom Masterslice Synthesizer”,in Proceedings of the Third International Conference on ASIC, 386-388, August 1998.

[4] Chenlan、Zhimin Tang,“Delay Model for Deep Submicron Wave Pipelined system”, osee, 29th,Dec.2000.


[5] Chenlan、Zhimin Tang,“Using Building Blocks Construct Deep Submicron Wave Pipelined system”, The First Portugal-China Workshop on Solid-State Circuits, pp101-102, Shanghai, China, Oct. 2000。

[6] Chenlan、Zhimin Tang,“A new kind of processor used for mobile computing”, The 7th. Union Computer Technology Workshop, pp1511-1516, Shantou, China, Novemember, 2000。

[7] Chenlan、Tang zhimin, “Application of the biggest time diffierence pipelining system in Single Chip system design”, The 6th graduate student academic colloquium paper collection, pp282-287, Dalian, July 2000.

[8] Chenlan、Zhimin Tang,“Design issues of deep submicron wave pipelining technology”,The 4th. IEEE International Conference on ASIC, Oct.2001,Shanghai。

[9] Chenlan、Tang zhimin, “The design technology of Soc”, p9-p16, 《Computer research and Development》, vol.39 No.1, Jan. 2002

[10] Hailong Jiao, Lan Chen, “Using OPC resued technologies for Reduced Standard Cell libray ”,Chinese Journal of Semiconductors,Vol. 29,No.5, May 2008,pp. 164-169.

[11] Hailong Jiao, Lan Chen, "Cellwise OPC Based on Reduced Standard Cell Library", Proc. of ISQED, 2008, pp. 810-814.

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