Name:WANG Guilei

Gender:Male

Title:Engineer

Nationality:P.R.China

Education:Doctor

E-Mail: wangguilei@ime.ac.cn

Department:Integrated Circuit Advanced Process R&D Center(ICAC)

Address:3 Beitucheng West Road, Chaoyang District, Beijing, PR China

Postcode:100029

Tel.:+86-10-82995563

Fax:+86-10-82995783

Education Background:

1. 2012.09－2016.07，University of Chinese Academy of Sciences,

Electronic and information Engineering，Doctor.

2. 2006.09－2009.07        Institute of Software and Microelectronics, Peking University, Microelectronics，Master.

3. 2001.09－2005.07        Beijing Institute of Petrol Chemical Technology, China，High polymer materials and Project，Bachelor.

Professional Experience:

1.2009.11－ Now        Institute of Microelectronics of Chinese Academy of Sciences /Integrated Circuit Advanced Process R&D Center(ICAC).

2. 2005.07－2009.10        Semiconductor Manufacturing International (Beijing) Corp.

Research Interests:

Semiconductor Material Growth and Device Fabrication

Publications:

[1]        Wang, G. L.，Moeen, M.，Abedin, A.，Kolahdouz, M.，Luo, J.，Qin, C. L.，Zhu, H. L.，Yan, J.，Yin, H.Z.，Li, J. F.，Zhao, C.，Radamson, H. H.，Optimization of SiGe selective epitaxy for source/drain engineering in 22nm node complementary metal-oxide semiconductor (CMOS)，Journal of Applied Physics，2013，114（12）

[2]        Wang, Guilei，Xu, Qiang，Yang, Tao，Luo, Jun，Xiang, Jinjuan，Xu, Jing，Xu, Gaobo，Li,Chunlong，Li, Junfeng，Yan, Jiang，Zhao, Chao，Chen, Dapeng，Ye, Tianchun，Application of atomic layer deposition Tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology，ECS transaction, San Francisco，P317-324，2013. 。

[3]        Wang, Guilei，Xu, Qiang，Yang, Tao，Xiang, Jinjuan，Xu, Jing，Gao, Jianfeng，Li, Chunlong，Li, Junfeng，Yan, Jiang，Chen, Dapeng，Ye, Tianchun，Zhao, Chao，Luo, Jun，Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology，ECS Journal of Solid State Science and Technology，2014，3（4）：P82-P85。

[4]        Wang, Guilei，Ahmad Abedin，Mahdi Moeen，Mohammadreza Kolahdouz，Jun Luo，Yiluan Guo，Tao Chen，Huaxiang Yin，Huilong Zhu，Junfeng Li，Chao Zhao，Henry H. Radamson，Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology，Solid-StateElectronics，2015，103：222-228。

[5]        Wang G, Moeen M, Abedin A, et al. Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs[J]. Solid-State Electronics, 2015, 114: 43-48.

[6]        Wang G, Qin C, Yin H, et al. Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14nm nodes FinFET technology[J]. Microelectronic Engineering, 2016..

[7] Wang G, Luo J, Qin C, et al. Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs[J]. ECS Transactions, 2016, 75(8): 273-279.

[8] Qin C, Wang G*, Kolahdouz M, et al. Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14nm node FinFETs[J]. Solid-State Electronics, 2016, 124: 10-15

Patents Application:

中国专利申请列表：

1.        王桂磊，尹海洲，半导体器件及其制造方法，201110029212.9

2.        王桂磊，李春龙，赵超，李俊峰，半导体器件及其制造方法，201110165241.8

3.        王桂磊，李春龙，赵超，李俊峰，半导体器件及其制造方法，201110165239.0

4.        王桂磊，李俊峰，赵超，消除接触孔工艺中桥接的方法，201110208407.X

5.        王桂磊，杨涛，一种提高浅沟槽隔离化学机械平坦化均匀性方法和设备，201110257878.X

6.        王桂磊，杨涛，李俊峰，赵超，一种提高浅沟槽隔离化学机械平坦化均匀性方法1，201110257855.9

7.        王桂磊，半导体器件及其制造方法，201110303593.5

8.        王桂磊，半导体器件及其制造方法，201110394014.2

9.        王桂磊，低温高覆盖性侧墙制造方法，201110433694.4

10.        王桂磊，崔虎山，赵超，半导体器件及其制造方法，201210162593.2

11.        王桂磊，李俊峰，赵超，半导体器件及其制造方法，201210273721.0

12.        王桂磊，李俊峰，赵超，半导体器件及其制造方法，201210345742.9

13.        王桂磊，杨涛，徐强，闫江，李俊峰，赵超        半导体器件及其制造方201210424681.5

14.        王桂磊，徐强，杨涛，闫江，李俊峰，赵超，半导体器件及其制造方法，201210473032.4

15.        王桂磊，秦长亮，李俊峰，赵超，氮化硅制造方法，201210473382.0

16.        王桂磊，朱慧珑，半导体器件制造方法，201310073320.5

17.        王桂磊，赵超，一种自然氧化层的去除方法，201310409612.1

18.        王桂磊，赵超，一种纯锗外延生长方法，201410081494.0

19.        王桂磊，赵超，徐强，杨涛，        一种半导体器件及其制造方法，201410089112.9

20.        王桂磊，赵超，徐强，陈韬，杨涛，李俊峰        一种半导体器件的制造方法，201410141701.7

21.        王桂磊，李俊峰，刘金彪，赵超，一种半导体器件的制造方法，201410196176.9

22.        王桂磊，崔虎山，殷华湘，李俊峰，朱慧珑，赵超， 半导体器件及其制造方法，201410328588.3

23.        王桂磊，殷华湘，赵超，半导体器件制造方法，201410328581.1

24.        王桂磊， 李俊峰，赵超，半导体器件制造方法，201410360703.5

25.        王桂磊， 李俊峰，赵超，半导体器件制造方法，201410360690.1

26.        王桂磊，崔虎山，殷华湘，李俊峰，朱慧珑，赵超，半导体器件及其制造方法，201410398357.X

27.        王桂磊，赵超，徐强，陈韬，杨涛，李俊峰，半导体器件及其制造方法，201410397828.5

28.        王桂磊，崔虎山，殷华湘，李俊峰，赵超，一种FinFet器件源漏外延前自然氧化层的去除方法，201410601934.0

29.        王桂磊，崔虎山，殷华湘，李俊峰，赵超，一种FinFet器件源漏外延前自然氧化层的去除方法，201410601931.7

30.        王桂磊，刘金彪，李俊峰，半导体器件制造方法，201410685729.7

31.        王桂磊，崔虎山，殷华湘，李俊峰，赵超，一种FinFet器件源漏外延设备及方法，201510028853.0

32.        王桂磊， 刘金彪，李俊峰，赵超，        半导体器件的制造方法        201510271246.7

33.        王桂磊， 刘金彪，高建峰，李俊峰，赵超，半导体器件的制造方法，201510351481.5

34.        王桂磊，Henry.H.Radamson，罗军，李俊峰，赵超，衬底及其制造方法，201510708606.5

35.        王桂磊，张严波，殷华湘，李俊峰，赵超，一种调节鳍体形貌的方法，201510708528.9

36.        王桂磊， Henry.H.Radamson，罗军,李俊峰，赵超， 衬底及其制造方法，201510708519.X

国际专利申请列表：

1.        王桂磊，尹海洲，Semiconductor Device and Manufacturing Method thereof，13/320,581

2.        王桂磊，李春龙，赵超，SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME，        13/497,744

3.        王桂磊，李俊峰，赵超，METHOD FOR ELIMINATING CONTACT BRIDGE IN CONTACT HOLE PROCESS，13/497,768

4.        王桂磊，李春龙，赵超，SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME，13/582,432

5.        王桂磊，SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME，13/582,433

6.        王桂磊，崔虎山; 赵超，SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME，13/878,524

7.        王桂磊，Semiconductor Device and Method for Manufacturing the Same，14/361,692

8.        王桂磊，刘金彪，李俊峰，METHODS FOR MANUFACURING SEMICONDUCTOR DEVICES，14/662,963

9.        王桂磊, 李俊峰, 刘金彪, 赵超，METHOD FOR MANUFACTURING SEMICONDUCNTOR DEVICE        14/698,624

10.        王桂磊, 刘金彪, 高建峰, 李俊峰, 赵超，        METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE，        14/838,628

Projects and Subjects Participated:

1. Chinese Academy of Sciences equipment function development technology innovation project: for MOCVD in-situ monitoring of thin film crystal quality and thickness of the reflectometer transformation, in research.

2. National key R & D project: semiconductor quantum chip project, a high-quality silicon-based semiconductor quantum chip materials, 2016YFA0301701, in research.