
Name | Feng Yan | Gender | Female |
Title | | Nationality | China |
Education | Doctor | E-Mail | fengyan@ime.ac.cn |
Department | EDA Center |
Address | 3 Beitucheng West Road, Chaoyang District, Beijing, PR China | Postcode | 100029 |
Tel | 010-82995646-813 | Fax | 010-62362261 |
Education Background |
1999.09-2003.07 B.S. degree in School of Physical Science and Technology, Lanzhou University. 2003.09-2006.07 M.E. degree in School of Physical Science and Technology,Lanzhou University. 2014.09-2019.07 D.E. degree in Institute of Microelectronics of the Chinese Academy of Sciences. |
Professional Experience |
2006.07-2008.07 Celestial (Beijing) Technology Co., Ltd. 2008.07-2017.04 Institute of Microelectronics of Chinese Academy of Science, Assistant Professor. 2017.04-present Institute of Microelectronics of Chinese Academy of Science, Senior Engineer. |
Publications |
[1] CHEN Lan, FENG Yan, Zhao Xin-chao, et al. GJB 7715-2012 General Requirements for Military Integrated Circuit IP Core [S]. [2] FENG Yan, CHEN Lan, Zhao Xin-chao, et al. Standards System on Military Integrated Circuit IP Core[J]. Military Standardization, 2014.2:30-32,38. [3] FENG Yan, CHEN Lan, WAND Dong, et al. Design and Verification of IP Core Test Wrapper Based on IEEE 1500 Standard[J], Microelectronics and computer, 2016,33(7):110-114. [4] MA Juan, CHEN Lan, FENG Yan, et al. The Research of IP Quality Evaluation Method for SoC Integration[J]. Microelectronics,2014,44(4): 555-558,564. [5] PENG Zhi-cong, CHEN Lan, FENG Yan, et al. Research of On-Chip Sine Stimulus Based on Sigma-Delta Modulation Techniques[J]. Microelectronics and computer, 2015,32(11):137-141. [6] Zhao Xinchao, Chen Lan, Feng Yan, et al. Design and verification of UART IP core based on hybrid prototyping platform [J]. Application of Electronic Technique, 2015,41(10):39-42 [7] Wang Dong, Chen Lan, Feng Yan. Analysis of key common technologies in military IP core standards system[J]. Application of Electronic Technique, 2016,42(9):24-28. [8] Wang Dong, Chen Lan, Feng Yan. Design of a Current-Steering DAC IP Core Based on 40 nm CMOS Process[J]. Microelectronics and computer, 2017,34(2): 25-29. [9] PENG Zhi-cong, CHEN Lan, FENG Yan, et al. Transaction Level Modeling of IEEE 802.3 MAC for Different Use Cases[J]. Microelectronics and computer, 2017,34(7): 56-59,64. |
Research Interests |
IP standardization and common technology, IP/SoC Design and Verification, Hardware Security of Integrated Circuit |
Projects and Subjects Participated |
As a main member: 1) The standardization program of key domestic hardware and software; 2) The pre-research of microelectronics in the 12th Five-Year Plan; 3) Some major national science and technology projects. |
Patents Application |
[1] FENG Yan, CHEN Lan. “Design method and device of test wrapper”, Patent authorization number: ZL 201610289656.9. [2] FENG Yan, CHEN Lan, WANG Dong. “A test wrapper device and its design method for embedded cores”, Patent authorization number: ZL 201510729220.2. [3] FENG Yan, CHEN Lan. “Built-in self-test method, device and system on-chip”, Patent authorization number: ZL 201510062392.9. [4] FENG Yan, CHEN Lan. “A Pulse-Widen Circuit and Method”, Patent authorization number: ZL 201610957975.2. [5] FENG Yan, CHEN Lan. “Clock control device and System on-chip including the clock control device”, Patent authorization number: ZL 201110388136.0. [6] FENG Yan, CHEN Lan. “Bus Interface Conversion Method and Bus Bridge Device”, Patent Authorization Number: ZL 201210175090.9. [7] PENG Zhi-cong, CHEN Lan, FENG Yan. “Bit stream selection method in memory-based on-chip Sigma-Delta analog excitation generation method”, Patent Authorization Number: ZL 201410799882.2. [8] LIU Zhen-chao, CHEN Lan, FENG Yan, et al. “ADC built-in self-test circuit and test method in SoC”, Patent Authorization Number: ZL 201610065972.8. [9] ZHANG Ting, CHEN Lan, FENG Yan. “A Fast Fourier Transform Processor”, Patent Authorization Number: 201110326494.9. [10] ZHANG Ting, CHEN Lan, FENG Yan. “Co-Bus Verification Method and System Based on System Verilog Assertions and Tasks, Patent Authorization Number: 201110390469.7. [11] ZHANG Ting, CHEN Lan, FENG Yan. “A Pipelined FFT Processor”, Patent Authorization Number: 201310150973.9. [12] WANG Dong, CHEN Lan, FENG Yan. “A Self-biased Current Source”, Patent Authorization Number: 201210575839.9. [13] FENG Yan, CHEN Lan. “A Test Method of IP cores based on test wrapper”, Patent Application Number: 201610289946.3. [14] FENG Yan, CHEN Lan. “Design Method and Device of Test Wrapper”, Patent Application Number: 201610289656.9. [15] FENG Yan, CHEN Lan. “Test Pattern Translation Method and Test Wrapper Device of cores”, Patent Application Number: 201610652013.6. [16]FENG Yan, CHEN Lan. “A Scan Test Execution Method, Device and System”, Patent Application Number: 201910227950.0. |
Honor |
Chen Lan, Feng Yan, et al. Third Prize of China Standard Innovation Contribution Award 2018. |